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Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for cost-efficient reliable design. A major step to accurately estimate a circuit SER is the computation of failure probability, which requires the computation of three derating factors, namely logical, electrical, and timing derating. The unified treatment of these derating factors is crucial to obtain accurate failure probability. Existing SER estimation techniques are either unscalable to large circuits or inaccurate due to lack of unified treatment of all derating factors. In this paper, we present fast and efficient algorithms to estimate SERs of circuit components in the presence of single... 

Time-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware-redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique... 

Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on... 

Time-interleaved analog to digital converters (TI-ADC) offer high sampling rates by passing the input signal through C parallel low-rate ADCs. We can achieve C-times the sampling rate of a single ADC if all the shifts between the channels are identical. In practice, however, it is not possible to avoid mismatch among shifts. Besides, the samples are also subject to jitter noise. In this paper, we propose a blind method to mitigate the joint effects of sampling jitter and shift mismatch in the TI-ADC structure. We assume the input signal to be bandlimited and incorporate the jitter via a stochastic model. Next, we derive an approximate model based on a first-order Taylor series and use an... 

Recently, an increasing concern has been raised about turn-to-turn faults (TTFs) in power transformers, because these faults can lead to severe transformer insulation failure and consequently, its outage. Generally, it is impossible to experimentally analyze the transformer behavior under such faults, since the implementation of those experiments may be substantially destructive. Therefore, computer-aided models should be developed to investigate the performance of transformer protective relays under turn-to-turn faults. So far, existing transformer models are mainly formulated to implement in the EMTP-based softwares. However, most of power system protection engineers and researchers... 

This letter investigates the problem of threedimensional (3-D) target localization in multiple-input multipleoutput (MIMO) radars with distributed antennas, using hybrid timedelay (TD) and angle of arrival (AOA) measurements. We propose a closed-form positioning method based on weighted least squares (WLS) estimation. The proposed estimator is shown theoretically to achieve the Cramer-Rao lower bound (CRLB) under mild noise conditions. Numerical simulations also verify the theoretical developments. IEEE  

Simulation of large-scale nonlinear dynamical systems on hardware with a high resemblance to their mathematical equivalents has been always a challenge in engineering. This paper presents a novel current-input current-output circuit supporting a systematic synthesis procedure of log-domain circuits capable of computing bilateral dynamical systems with considerably low power consumption and acceptable precision. Here, the application of the method is demonstrated by synthesizing four different case studies: 1) a relatively complex 2-D nonlinear neuron model; 2) a chaotic 3-D nonlinear dynamical system Lorenz attractor having arbitrary solutions for certain parameters; 3) a 2-D nonlinear Hopf... 

The authors propose a new design for monolayer superconducting planar flux transformer integrated with a coplanar resonator serving as a gigahertz range tank circuit for high-Tc rf-SQUID magnetometers. Based on the proposed design, which is optimized using the finite element method, the transformer-resonator configuration is made of 200-nm-thick monolayer YBCO film on a crystalline LaAlO3 substrate. In this optimized design, the SQUID magnetometer is coupled through flip-chip configuration with the configuration providing high coupling coefficient between the devices. The design permits coupling of the rf signals to the SQUID efficiently, whereas the transformer is designed to couple the dc... 

This paper presents an analytical model for power harvester circuits used in Ultra-low power applications. Assuming that the MOS devices of the circuit fully operate in the Sub-threshold regime in both forward and reverse regions, closed-form equations for important properties of the rectifier circuit such as output voltage, efficiency and input resistance are derived. The model includes the effect of the compensation voltage on the circuit behavior. There is a good agreement between the simulation results and the model. In addition, the contour plots needed to simultaneously optimize the matching network and the rectifier circuit are derived by the resulting equations. A 50-Stage rectifier... 

Secure computation has obtained significant attention in the literature recently. Classic architectures usually use either the Garbled Circuit (GC) or the Goldreich-Micali-Wigderson (GMW) protocols. So far, to reduce the complexity of communications in these protocols, various methods have been proposed. The best known work in both methods reduces the communication up to almost 2k-bits (k is the symmetric security parameter) for each AND gate, and using XOR gate is free. In this paper, by combining GC and GMW, we propose a scheme in the semi-honest adversary model. This scheme requires an Oblivious Transfer (OT) and a 2-bit data transfer for each AND gate, keeping XOR gates free. The... 

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of... 

Fast and accurate fault detection is the primary step and one of the most important tasks in fault tolerant converters. In this paper, a fast and simple method is proposed to detect and diagnosis the faulty cell in a cascaded H-bridge multilevel inverter under a short circuit fault. In this method, the reference voltage is calculated using switching control pulses and DC-Link voltages. The comparison result of the output voltage and the reference voltage is used in conjunction with active cell pulses to detect the faulty cell. To achieve this goal, the cell which is active when the Fault signal turns to “0” is detected as the faulty cell. Furthermore, consideration of generating the active... 

Resolvers are widely used in the control of industrial inverter driven motors. Among different types of resolvers, disk-type wound-rotor resolvers have superior performance under mechanical faults. However, the rotary transformer's (RT's) presence in the inner side of the resolver's core leads to additional radial length. To overcome this problem, disk-type wound-rotor resolver without RT's core has been proposed. However, the optimization using time stepping finite-element method (TSFEM) is time consuming due to 3-D structure of this resolver. Accordingly, in this paper, an analytical model based on the magnetic equivalent circuit is proposed for the design and optimization process. The... 

Interfacial studies and band alignment engineering on the electron transport layer (ETL) play a key role for fabrication of high-performance perovskite solar cells (PSCs). Here, an amorphous layer of SnO2 (a-SnO2) between the TiO2 ETL and the perovskite absorber is inserted and the charge transport properties of the device are studied. The double-layer structure of TiO2 compact layer (c-TiO2) and a-SnO2 ETL leads to modification of interface energetics, resulting in improved charge collection and decreased carrier recombination in PSCs. The optimized device based on a-SnO2/c-TiO2 ETL shows a maximum power conversion efficiency (PCE) of 21.4% as compared to 19.33% for c-TiO2 based device.... 

In this paper, a fast and practical method is proposed for open-circuit (OC) fault diagnosis (FD) in a three-phase quasi-Z-source inverter (q-ZSI). Compared to the existing fast OC FD techniques in three-phase voltage-source inverters (VSIs), this method is more cost-effective since no ultra-fast processor or high-speed measurement is required. Additionally, the method is independent of the load condition. The proposed method is only applicable to Z-source family inverters and is based on observing the effect of shoot-through (SH) intervals on the system variables during switching periods. The proposed algorithm includes two consecutive stages: OC detection and fault location identification.... 

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of... 

A non-linear robust adaptive bilateral impedance controller is proposed to provide the absolute stability of multi-DOF teleoperation systems with communication delays, in addition to the force and position tracking performance. The proposed controller realises two desired (or reference) impedance models for the master and slave robots using a new non-linear robust version of the model reference adaptive control scheme. Using the absolute stability criterion, the robustness condition of the teleoperation system against communication delays is obtained, resulting in suitable adjustments of parameter values in the desired impedance models. In addition, using the Lyapunov stability theorem, the... 

Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we present a Resistive Random Access Memory RRAM-based FPGA architecture employing efficient Switch Box (SB) and Look-Up Table (LUT) designs with programming circuitry integrated in both SB and LUT designs that creates area and power efficient programmable components while precluding performance... 

The limited value of the insolated-gate bipolar transistors (IGBTs) blocking voltage is an important issue for applying these devices to the high-voltage power converters. An effective solution is to use a series configuration of these devices in order to achieve higher voltage ratings in addition to save the interesting features such as fast rising time. To reach this goal, acceptable equal voltage sharing for the IGBTs are provided by the series stacking schemes in the normal operation.However, a considerable difference in their voltage level will be occurred in the short-circuit condition. Although the IGBT can withstand the short-circuit current in a defined time, the occurred high... 

In this paper a new approach is developed to stabilize descriptor systems with time-delay, while time-delay can belong to a given interval. This approach takes the advantages of system's singularity to simplify the model and uses the so-called Rekasius substitution to compute the controller parameters in a way that the asymptotic stability of the closed-loop system in the given interval of the delay can be guaranteed. Finally, a numerical example is provided to evaluate the proposed method's effectiveness. © 2017 IEEE