Designing a MIPS Processor Using Transactional Level Modeling Tools

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Rahimzadeh Rufuie, Mehrdad | 2010

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Type of Document: M.Sc. Thesis
Language: English
Document No: 40138 (55)
University: Sharif University of Technology, International Campus, Kish Island
Department: Science and Engineering
Advisor(s): Vosoughi Vahdat, Bijan; Mortazavi, Mohammad
Abstract:
Processor cores in embedded applications is one the of important part of System-on-Chip designs. Among the most successful (Reduced Instruction Set Computer) RISC cores are the (Million Instruction Per Second) MIPS processors used in applications such as DVD, automotive, broadband access, networking, etc. In this work we have designed and verified Transaction Level Modeling (TLM) architecture of the MIPS in SystemC TLM2.0. The TLM in SystemC is adopted so that abstract data types can be used for higher (abstract) level modeling and faster simulation design. We implemented the processor such that the instruction and data caches contain all the necessary instructions and data to eliminate complex memory access management
Keywords:
C Programming Language ; Reduced Instruction Set Computer (RISC) ; System-on-Chip ; Transactional Level Modeling

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