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Design and Evaluation of a Reliable Switching Method for Network-on-Chips

Allivand, Yassin | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: English
  3. Document No: 42824 (52)
  4. University: Sharif University of Technology, International Campus, Kish Island
  5. Department: Science and Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. Growth in the number of transistors on a single die has made Network-on-Chips more vulnerable to transient faults such as Crosstalks, SEUs and MBUs. The aim of this thesis is to evaluate the effects of virtual channel structures on the performance and the power consumptions of NoCs in the presence of transient faults. Evaluations have been carried out by different switch architectures and experimental conditions, i.e., different traffic and fault injection rates. In this regard, we have measured the power and latency of the switch both in different buffer allocation mechanisms and different switching methods. The evaluated switching methods in this work vary from Virtual Cut through (VCT) to store and forward method and wormhole switching method. All the experiments provided in this thesis have been carried out by means of Xmulator, an accurate cycle NoC simulator, along with Orion path. As simulation results reveal, in the high traffic rates, the increasing number of virtual channels leads to reduction in terms of latency. Similarly, in the low traffic rates, as a result of multiplexing time to choose the best virtual channel, the latency will be increased. Thus, facing fault occurrence, the proper way is to use a configured virtual cut through by adding or removing virtual channels. The virtual channel buffers take more time to detect and correct the faulty bits. Also, by duplicating the channels in case of hardware redundancies, more reliability chances are achieved in on-chip circuits as well
  9. Keywords:
  10. Reliability ; Dynamic Reconfiguration ; Network-on-Chip (NOC) ; Switching Method

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