Loading...

Design of Fault-tolerance Mechanisms for Soft Multiprocessors

Zabihi, Masoumeh | 2013

588 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44768 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. Increasing complexity of embedded systems and the need for more computation powerhave directed designers toward using of multiprocessors. SRAM-based FPGAs are suitable platforms for implementation of multiprocessors due to thier low cost, fast time-to-market and re-configurability. FPGA-based multiprocessors are known as soft multiprocessors. The large area of SRAM-based FPGAs is occupied by configuration bits. Configuration bits are vulnerable to high energy particles that can lead to soft errors. In this regards, it is of decisive importance to protect soft multiprocessors against soft errors. This thesis proposes a fault-tolerant method for soft multiprocessors that can detect and correctboth SEUs (Single Event Upsets) and SEMUs (Single Event Multiple Upsets) in the configuration bits. The proposed method is based on three mechanisms: 1) fault detection; 2) fault correction and 3) fault recovery. To detect errors, a scheduling mechanism is implemented which selects a subset of tasks for replications. By executing replicas, the scheduling mechanism is able to detect errors in all processors. To correct errors, a reconfiguration mechanism is run. Then, in order to recover errors,the processors restore to the state where all processors are verified in term of correct operation. The proposed method is analytically and experimentally evaluated. The analytical results show that about all errors can be detected and corrected.To evaluate the performance of the proposed method, a set of standard task graphs is applied. The results show that the performance overhead for systems with four and eight processors is about 20% and 15%, respectively, While the lockstep method with the same reliability incurs 90% and 45% performance overhead, respectively.Also, the proposed method imposes no area overhead to system
  9. Keywords:
  10. Scheduling ; Soft Multiprocessor ; Field Programmable Gate Array (FPGA) ; Fault Tolerance

 Digital Object List

 Bookmark