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A Non-volatile Processor Cache Architecture with Multi-retention Time Intervals

Rezaei Firuzkuhi, Mahsa | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44796 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. Traditional multi-level SRAM-based cache hierarchies, especially in the context of chip multiprocessors (CMPs), present many challenges in area requirements, power consumption, and design complexity. STT-RAM has received increasing attention because of its attractive features:good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/4 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. In parti cular, our design use STT-RAM cells with various data retention time and write performances, made possible by different magnetic tunnelling junction (MTJ) designs. We propose a run-time strategy for managing writes between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. To this end, we assume that each cache set is decomposed into limited low retention STT-RAM lines and large number of high retention STT-RAM lines. Low retention STT-RAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into high retention STT-RAM array. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into low retention STT-RAM lines during system operation. Therefore, the achieved cache architecture has large capacity and consumes near zero leakage energy using STT-RAM technology; while dynamic write energy,acceptable write latency, and long lifetime is guaranteed via low retention STT-RAM array. Results of full-system simulation for a quad-core CMP running PARSEC-2 and SPEC CPU2006 benchmark suits confirm an average of 7% improvement in cache performance, an average of 20% improvement in last levele cache average access latency and more than 70% reduction in cache power consumption when compared to baseline configurations
  9. Keywords:
  10. Efficiency ; Power Consumption ; Spin Transfer Torque-Magnetic (STT-MRAM) ; Retention Time ; Hybrid Cache Architecture

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