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Analytical Modeling and Performance Evaluation for Networks-on-Chip with Quality-of-Service Guarantee
Rahmati, Dara | 2013
743
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- Type of Document: Ph.D. Dissertation
- Language: Farsi
- Document No: 45420 (19)
- University: Sharif University of Technology
- Department: Computer Engineering Department
- Advisor(s): Sarbazi-azad, Hamid
- Abstract:
- Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. Average Delay and Average Bandwidth are historically the popular metrics used to evaluate the performance of an on-chip network. For RT communication, guaranteeing Minimum Delay and Maximum Bandwidth (performance bounds) which are known as the metrics for Quality-of-Service (QoS) have been at great importance during recent years. Networks-on-chip are classified to Best-Effort (BE) and Guaranteed-Service (GS) networks. Packets are processed without any precedence in BE networks, while there are special hardware and controlling mechanisms to distinguish between higher or lower priority packets in GS networks. Because of the complexity and overheads in GS networks, most the NoCs have been of BE type nowadays. On the other hand due to complex nature of packet contention, there has been no analytical model to properly calculate performance bounds in these
networks. In this dissertation accurate analytical models have been proposed for this purpose. Another objective of the dissertation is to propose methodologies to design GS networks with low hardware complexity and low overhead just like an equivalent BE network, which still distinguishes the priority of the packets. To address this, a new class-based arbitration method is introduced. The method is derived from the basic round-robin arbitration. The proposed models or methods are all demonstrated, evaluated and verified accordingly - Keywords:
- Network-on-Chip (NOC) ; Real-Time Procces ; Topology ; Routing ; Switchy ; Efficiency ; Service Quality
