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Reliability Improvement in Network on Chip against Soft Errors Considering Multiple Bit Upsets

Zamani Sabzi, Hadi | 2014

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 46143 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. Network on chips (NoCs) have emerged as a feasible solution to handle growing number of communicating components on a single chip. The scalability of chipsincreases the probability of errors and making the reliability a major issue in scaling chips. Soft errors and crosstalk faults are the most important fault sources which can decrease the reliability of NoCs. The probability of Soft errors has increased by about 6 to 7 times by scaling from 130 to 30 nm technology. Since buffers occupy in about 40% to 90% of the area of switches, the probability of a multiple bit upset in a switch buffers is noticeable. In NoC architecture, a packet is broken down into multiple flow control units called flits. These flits are sent and received in the communication channels by means of links between the cores. Every arriving flit in each router is temporary stored in input and/or output buffers until resources are freed. During this flit transmission, data integrity can be treated by soft errors or crosstalk faults.Reliability of these stored flits in buffers is seriously treated by soft errors including SEUs and MBUs. In this work, deflection aware mechanism combined with simple information redundancies are employed to tolerate the soft errors and crosstalk faults in header flits. And also,splitted flit interleaving is used beside the error detection/correction codes like hamming codes to tolerate burst errors in body and tail flits. The methods and mechanisms are evaluated in two levels. In circuit level, the proposed mechanisms overheads are reported by design compiler using 45 nm technology.And also, we evaluate the efficiency ofproposedmethods using the BookSim 2.0 interconnection network simulator. Simulations are performed on an 8×8 2D mesh network.All network channels are128 bits wide and Packets are routed using Dimension-Order routing (DOR). The efficiency of the proposed methods in error detection/correction is evaluated by simulator written inC++ and MATLAB Simulink.The results show that,the proposed method achieves high reliability while maintaining performance efficiency
  9. Keywords:
  10. Reliability ; Soft Error ; Network-on-Chip (NOC) ; Deflection Aware Mechanism ; Splitted Flit Interleaving

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