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An Aging Aware Routing Algorithm for 3D-NoC

Mirizadeh, Danial | 2014

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 46665 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shaahin
  7. Abstract:
  8. Combining the concept of Network-on-Chip (NoC) with three dimensional integrated circuits technology on 3D NoC enables reduction of propagation delay, interconnect power consumption, and die area, as well as increase in system operational bandwidth. Nevertheless, reducing the feature size of semiconductor technologies has raised certain aging mechanisms, like Negative Bias Temperature Instability (NBTI) and Electromigration, as the main reasons for reduction in reliability and lifetime of NoCs. Reduction in die area results in an increase in power density of the chip, which exacerbates temperature-related concerns of 3D NoCs compared to 2D NoCs. Thus, the aging mechanisms that are directly related to the chip temperature are aggravated. In this dissertation, a novel NoC architecture is proposed. Employing bidirectional links, a two-phase routing algorithm, and considering the temperature of each router and the number of transmitted and received packets on each link, the proposed architecture puts forward a routing algorithm with the objective of reducing electromigration and extending the lifetime of NoC links. Simulation results show that the proposed method extends the lifetime of the NoC by 4.1 up to 16.4 times compared to the XYZ algorithm. Three types of synthetic traffics are used in simulations. Furthermore, the packet injection rate is chosen such that the chip temperature never exceeds 122 degrees Celsius. The proposed architecture imposes a maximum network latency overhead of 8.5 percent, and an increase of 4.9 percent in power consumption
  9. Keywords:
  10. Reliability ; Three Dimentional Network on Chip (NOC) ; Aging ; Routing Algorithm ; Electromigration ; Bidirectional Links

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