Reliability Enhancement of Cache Memories Based on Non-Volatile Cells

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Ghaemi, Golsana | 2015

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 47584 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Miremadi, Ghassem
Abstract:
Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this study proposes an STT-RAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bit-lines of the tag update more. The SRAM part handles the updates in the bit-lines which their lifetime is less than the desired lifetime and the rest of bit-lines will be implemented by STT-RAM cells. The proposed architecture is evaluated by the gem5 simulator running MiBench benchmark suits. The evaluation results demonstrate that LATED not only met the 5-year desired lifetime, but also could make up to 70% saving in static energy consumption of tag array in comparison to SRAM one
Keywords:
Reliability ; Cache Memory ; Nonvolatile Memory ; Endurance ; Tag Memory

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