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Vulnerability modeling of cryptographic hardware to power analysis attacks

Moradi, A ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1016/j.vlsi.2009.01.001
  3. Publisher: 2009
  4. Abstract:
  5. Designers and manufacturers of cryptographic devices are always worried about the vulnerability of their implementations in the presence of power analysis attacks. This article can be categorized into two parts. In the first part, two parameters are proposed to improve the accuracy of the latest hypothetical power consumption model, so-called toggle-count model, which is used in power analysis attacks. Comparison between our proposed model and the toggle-count model demonstrates a great advance, i.e., 16%, in the similarity of hypothetical power values to the corresponding values obtained by an analog simulation. It is supposed that the attacker would be able to build such an accurate power model. Thus, in the second part of this article we aim at evaluating the vulnerability of implementations to power analysis attacks which make use of our proposed power model. Simple power analysis, various types of differential power analysis, and correlation power analysis are taken into account. Then, some techniques are proposed to examine the vulnerability of implementations to such kinds of power analysis attacks. © 2009 Elsevier B.V. All rights reserved
  6. Keywords:
  7. DPA ; Glitches ; SPA ; Toggle-count DPA ; Vulnerability ; DPA ; Glitches ; SPA ; Toggle-count DPA ; Vulnerability
  8. Source: Integration, the VLSI Journal ; Volume 42, Issue 4 , 2009 , Pages 468-478 ; 01679260 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0167926009000042