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Design and Implementation of a Linear, 1 Watt, High Efficiency Power Amplifier with Controllable Output Power for UHF-RFID Application

Sadeghi, Sanaz | 2018

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 50475 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifbakhtiar, Mehrdad
  7. Abstract:
  8. Design and implementation of an efficient, 1 Watt, linear power amplifier (PA) with CMOS technology for UHF-RFID applications is presented in this thesis. Poor quality factor of inductors, high substrate noise and low breakdown voltage of CMOS, makes the implementation of Watt-level PAs challenging on this technology. Also the trade-off between linearity and efficiency, further hardens achieving an efficient high power linear PA. So the literature was reviewed first to come up with the appropriate structure of a linearized efficient PA. Afterwards, the structure was reformed and optimized for the application mentioned above with reasonable stability margins. Baseband relevant blocks were also designed and simulated. The whole transmitter was laid out, taking into account special considerations aroused from the high power of the PA. Post layout simulations of the system with a power supply of 1.8 V showed a peak output power of 30.93 dBm with 58% Drain efficiency at the frequency of 900 MHz de-embedding Balun losses. Assuming a Balun with less than 0.9 dB attenuation, the peak output power will be more than 30 dBm with at least 47% Drain efficiency. Also symbols, satisfying multiple and dense mask in simulations, were presented
  9. Keywords:
  10. Linearization ; Efficiency ; Power Amplifier ; Power Output ; Radio Frequency Identification (RFID) ; Ultra High Frequency (UHF)-Radio Frequency Identification (RFID)Transciever

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