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A-CACHE: alternating cache allocation to conduct higher endurance in nvm-based caches

Farbeh, H ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSII.2018.2881175
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. Recent developments in Non-Volatile Memories (NVMs) have introduced them as an alternative for SRAMs in on-chip caches. Besides the promising features of NVMs, e.g., near-zero leakage power, immunity to radiation-induced particle strike, and higher density, a major drawback of NVM-based caches is their short lifetime due to limited write endurance. This paper first reveals that in L1 caches, the lifetime of data-cache (D-cache) is about 472x shorter than that of instruction-cache (I-cache) due to extreme imbalance write stress between the two. Then, we propose a technique, so-called Alternating Cache Allocation to Conduct Higher Endurance (A-CACHE), to improve the lifetime of frequently-written D-cache by exploiting rarely-written I-cache. The key idea in A-CACHE is to alternate the locations of storing instructions and data between I-cache and D-cache. The evaluation results show that A-CACHE improves the lifetime of the cache by 83% with negligible overheads. IEEE
  6. Keywords:
  7. Endurance ; Microprocessors ; Non-volatile memory (NVM) ; Nonvolatile memory ; Random access memory ; Resource management ; System-on-chip ; Wear-leveling ; Computer architecture ; Computer resource management ; Computer testing ; Durability ; Microprocessor chips ; Nonvolatile storage ; Static random access storage ; Benchmark testing ; L1 caches ; Lifetime ; Wear leveling ; Cache memory
  8. Source: IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8533424