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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 55094 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Sharif Bakhtiar, Mehrdad
- Abstract:
- In this thesis, a wideband multi-standard digital transmitter based on the multi-path architecture has been designed in 65-nm CMOS process. Moreover, the effect of phase error of the clocks on the output specifications of this multi-path transmitter has been analyzed, and based on the derived theoretical equations, circuit-level solutions for the correction of these errors have been proposed. In addition to the circuit-level solutions for error correction of the clocks, a general setup for calibration of the multi-path transmitter has been presented. Also, several software-based algorithms for the calibration of the transmitter have been studied and their validity has been verified using both system and circuit-level simulations. In addition to the conventional DPD algorithms, an Artificial neural network based calibration algorithm also capable of compensating the memory effect has been proposed and the validity of its performance has been verified using simulation. Circuit-level simulations at the carrier frequency of 2.5 GHz, verify a maximum output power of 12.8 dBm, maximum power efficiency of 13.11%, harmonic rejection ratio of better than 42.1 dBc, and error vector magnitude of -42.5 dB using calibrations. Furthermore, the operating RF frequency range of the transmitter is from 200 MHz to 6 GHz while the amount of harmonic rejection ratio for all harmonics is better than -40 dBc.
- Keywords:
- Wideband ; Calibration ; Digital Predistortion ; Artificial Neural Network ; Memory Effect ; Multistandard Transmitter ; Multi-Path Architecture ; 5th Generation Cellular Network
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