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Design of a Non-Bianry Analog to Digital Converterfor Impantable Neural Recording Microsystem

Eslampanah Sendi, Mohammad Sadegh | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43356 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifkhani, Mohammad; Sodagar, Amir Masoud
  7. Abstract:
  8. A new structure of implantable neural recording microsystem base on multiple valued logic (MVL) has been proposed. MVL is a new idea for reduction of occupied area and the power consumption of microelectronic. In another side, in implantable microsystems , occupied area and power consumption by this type of micro systems is a challenging problem in this field. Therefore, the problem of power consumption and occupied area can introduce as a prime stage of suggested microsystem completed design of convertor of analog to digital in usage of multiple level in this micro system worked. Design of convertor of analog to digital is a convertor of quaternary successive approximation. And also, different idea in circuits in various fields such as multiple valued logic circuits, convertor of digital to analog and modulator for applications of wireless communication in recording of neural signal has been suggested. In field of multiple level circuits, a low power, CMOS compatible structure has been suggested. A quaternary inverter and a quaternary latch has been designed by this configuration. In addition quaternary latched comparator for the first time has been proposed. Mentioned circuit is based on the suggested instruction. For calculation of static noise margin (SNM) in quaternary invertors, triple butterfly curve has been introduced, the SNM of the designed inverter is 0.22V at 1.8V supply voltage. Also a total structure of digital to analog has been suggested.According to the total instruction, a 3 digit Quaternary DAC and a 4 digit ternary DAC has been designed and lay out.In simulation the maximum INL and DNL for 3-digit quaternary DAC are (-0.15, +0.1)LSB and (-0.2, +0.35)LSB respectively. The maximum INL and DNL for 4-digit Tenary DAC are (-0.35, +0.35)LSB and (-0.1, +0.4)LSB respectively. A test circuit for these converters is designed and layouted and the area of it is 490µm×970µm .In design of the successive approximation analog to digital quaternary, a algorithm named quaternary search has been proposed and implemented. Finally a channel model for suggested microsystem was proposed. Therefore, surveying of transmitting signal insigne in area of human brain has been considered, that by this survey the optimization of frequency band for wireless communication in application of neural signal record has been proposed, Also a 4FSK modulator has been designed.
  9. Keywords:
  10. Digital to Analog Converter ; Multiple Valued Logic ; Implantable Microsystem

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