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CLASS: Combined logic and architectural soft error sensitivity analysis

Ebrahimi, M ; Sharif University of Technology | 2013

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  1. Type of Document: Article
  2. DOI: 10.1109/ASPDAC.2013.6509664
  3. Publisher: 2013
  4. Abstract:
  5. With continuous technology downscaling, the rate of radiation induced soft errors is rapidly increasing. Fast and accurate soft error vulnerability analysis in early design stages plays an important role in cost-effective reliability improvement. However, existing solutions are suitable for either regular (a.k.a address-based such as memory hierarchy) or irregular (random logic such as functional units and control logic) structures, failing to provide an accurate system-level analysis. In this paper, we propose a hybrid approach integrating architecture-level and logic-level techniques to accurately estimate the vulnerability of all regular and irregular structures within a microprocessor. All error propagation and masking scenarios are carefully handled among these structures. We have evaluated the vulnerability of the OR1200 processor using the proposed approach. Comparison with statistical fault injection shows an average inaccuracy of less than 7% with five orders of magnitude improvement in runtime
  6. Keywords:
  7. Early design stages ; Error propagation ; Irregular structures ; Orders of magnitude ; Radiation-induced ; Reliability improvement ; System-level analysis ; Vulnerability analysis ; Computer aided design ; Error correction ; Microprocessor chips
  8. Source: Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC ; 2013 , Pages 601-607 ; 9781467330299 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6509664