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Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology

Javidan, J ; Sharif University of Technology | 2012

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  1. Type of Document: Article
  2. DOI: 10.1002/cta.765
  3. Publisher: Wiley , 2012
  4. Abstract:
  5. This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires
  6. Keywords:
  7. System design ; Transmitter leakage ; Bonding pads ; Chip areas ; CMOS processs ; CMOS technology ; Design considerations ; Direct conversion receiver architecture ; Feedback structure ; M-Technologies ; Output power ; Passive RFID ; Power combiner ; Power gains ; Power-added efficiency ; RF front end ; RF front end circuits ; RFID readers ; Tx leakage ; UHF RFID ; Variable gain amplifiers ; CMOS integrated circuits ; Low noise amplifiers ; Power amplifiers ; Transmitters ; Systems analysis
  8. Source: International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN)
  9. URL: http://onlinelibrary.wiley.com/doi/10.1002/cta.765/abstract;jsessionid=E9D51482E9B9D65326675F8B5E5DFD36.f04t04