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Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization

Momtazpour, M

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  1. Type of Document: Article
  2. DOI: 10.1145/1973009.1973063
  3. Abstract:
  4. In nanometer-scale process technologies, the effects of process variations are observed in Multiprocessor System-on-Chips (MPSoC) in terms of variations in frequencies and leakage powers among the processors on the same chip as well as across different chips of the same design. Traditionally, worst-case values are assumed for these parameters and then a deterministic optimization technique is applied to the MPSoC application under design. We show that such worst-case-based approaches are not optimal with the increasing variation observed at system-level, and instead, statistical approaches should be employed. We consider the problem of simultaneously choosing MPSoC architecture and task allocation for energy optimization under a given performance constraint. Our experimental results on E3S benchmark suite show that the proposed statistical optimization technique can achieve 33.7% improvement on average over conventional worst-case-based techniques and up to 21.7 % improvement over best previously proposed statistical analysis technique
  5. Keywords:
  6. Architecture exploration ; Energy minimization ; MPSoC ; Process variation ; Task scheduling ; Task scheduling ; Computer architecture ; Lakes ; Multiprocessing systems ; Multitasking ; Optimization ; Scheduling ; Scheduling algorithms ; Microprocessor chips
  7. Source: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI ; 2011 , Pages 271-276 ; 9781450306676 (ISBN)
  8. URL: http://dl.acm.org/citation.cfm?doid=1973009.1973063