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- Type of Document: Article
- Abstract:
- To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode
- Keywords:
- Cell area ; Leakage current ; SRAM cell ; 65nm CMOS technology ; Bit lines ; Cell size ; CMOS technology ; Design rules ; Idle mode ; ITS data ; Nanoscaled ; Positive feedback ; Read/write operations ; Simulation result ; Transistor cells ; Cells ; CMOS integrated circuits ; Cytology ; Feedback ; Leakage currents ; Static random access storage
- Source: World Academy of Science, Engineering and Technology ; Volume 65 , 2010 , Pages 172-174 ; 2010376X (ISSN)
- URL: http://waset.org/Publications/?path=Publications&q=A+novel+nano-scaled+SRAM+cell&search=Search