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Temperature compensation in CMOS peaking current references

Eslampanah Sendi, M. S ; Sharif University of Technology | 2018

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSII.2018.2805832
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2018
  4. Abstract:
  5. In this brief, modifications to the peaking current reference with MOS transistors operating in the subthreshold and the strong inversion region has been proposed by means of which very small currents with immunity to temperature variations on a chip can be obtained. Temperature compensation can be done by adding a source degeneration resistor to the conventional peaking current source structure. Design examples are provided for both weak and strong inversion operations with output currents of 1.5 μA and 40 μ A with less than 4% and 10% variation over the span of-40 °C to +100 °C, respectively. A prototype of the circuit operating in the weak and strong inversion region is designed, simulated, and then fabricated in a TSMC 0.18-μ m process. Measurement results verify the functionality of the proposed structure. © 2004-2012 IEEE
  6. Keywords:
  7. Current source ; Peaking current reference ; Temperature coefficient ; CMOS integrated circuits ; Electric current measurement ; Monte Carlo methods ; Resistors ; Temperature measurement ; Circuits and systems ; Current reference ; Current sources ; MOS-FET ; Temperature compensation ; Temperature dependence ; Temperature distribution
  8. Source: IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 65, Issue 9 , 2018 , Pages 1139-1143 ; 15497747 (ISSN)
  9. URL: https://ieeexplore.ieee.org/abstract/document/8290961