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A secure and low-energy logic style using charge recovery approach

Khatir, M ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1145/1393921.1393990
  3. Publisher: 2008
  4. Abstract:
  5. The charge recovery logic families have been designed several years ago not in order to eliminate the side-channel leakage but to reduce the power consumption. However, in this article we present a new charge recovery logic style not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks especially against differential power analysis attacks. Our approach is a modified version of a classical charge recovery logic style namely 2N-2N2P. Simulation results show a significant improvement in DPA-resistance level as well as in power consumption reduction in comparison with 2N-2N2P and other DPA-resistant logic styles. Copyright 2008 ACM
  6. Keywords:
  7. Electric power utilization ; Energy efficiency ; Low power electronics ; Power electronics ; Signal analysis ; Cell level DPA-countermeasure ; Charge recoveries ; Charge recovery logic ; Differential power analysis ; Differential power analysis attacks ; High energy efficiencies ; Logic styles ; Low energies ; Power consumption ; Power consumption reductions ; Resistance levels ; Side channels ; Side-channel attack ; Simulation results ; Recovery
  8. Source: ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, 11 August 2008 through 13 August 2008 ; 2008 , Pages 259-264 ; 15334678 (ISSN); 9781605581095 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/5529043