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A novel zero-aware read-static-noise-margin-free SRAM Cell for high density and high speed cache application

Azizi Mazreah, A ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/ICSICT.2008.4734683
  3. Publisher: 2008
  4. Abstract:
  5. To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM cell using same design rules. Simulation result in standard 0.25μm CMOS technology shows purposed cell has correct operation during read/write and idle mode. The average delay of new cell is 20% smaller than a six-transistor SRAM cell. © 2008 IEEE
  6. Keywords:
  7. Average delays ; Bit lines ; Cell sizes ; Cmos technologies ; Design rules ; High densities ; High-speed ; Idle modes ; Its datum ; Positive feedbacks ; Read/write operations ; Simulation results ; SRAM cells ; Cells ; CMOS integrated circuits ; Feedback ; Integrated circuits ; Transistors ; Static random access storage
  8. Source: 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, Beijing, 20 October 2008 through 23 October 2008 ; 2008 , Pages 876-879 ; 9781424421855 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4734683