Loading...

Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing

Shahbazi, N ; Sharif University of Technology | 2007

413 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/ICPADS.2007.4447827
  3. Publisher: 2007
  4. Abstract:
  5. The widespread application of deep sub-micron and multilayer routing techniques makes the interconnection parasitic influence become the main factor to limit the performance of VLSI circuits. Therefore, fast and accurate 3D capacitance extraction is essential for ultra deep sub-micron design (UDSM) of integrated circuits. Parallel processing provides an approach to reducing the simulation turn-around time. In this paper, we present parallel formulations for 3D capacitance extraction based on P-FFT algorithm, on a personal computer (PC) or on a network of PCs. We implement both vector and parallel versions of 3D capacitance extraction algorithm simultaneously and evaluate our implementation quality in terms of speed up achieved. © 2007 IEEE
  6. Keywords:
  7. Capacitance ; Electronics industry ; Integrated circuits ; Microcomputers ; Parallel algorithms ; Personal computers ; 3D capacitance ; Capacitance extraction ; Deep-sub micron ; FFT algorithms ; International conferences ; Multi-layer routing ; Parallel and distributed systems ; Parallel processing ; Speed ups ; Turn-around time ; VLSI designs ; VLSI circuits
  8. Source: 13th International Conference on Parallel and Distributed Systems, ICPADS, Hsinchu, 5 December 2007 through 7 December 2007 ; Volume 2 , December , 2007 ; 15219097 (ISSN); 9781424418909 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4447827