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Optimum supply and threshold voltages and transistor sizing effects on low power SOI circuit design

Emadi, M ; Sharif University of Technology | 2006

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  1. Type of Document: Article
  2. DOI: 10.1109/APCCAS.2006.342461
  3. Publisher: 2006
  4. Abstract:
  5. In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1-1.5V and Vth=0-0.8V, are analyzed to find optimal Vdd and Vth BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and the formulations for finding the optimum gate sizing are also presented. Theses algorithms can be implemented in a CAD tool too. ©2006 IEEE
  6. Keywords:
  7. Delay circuits ; Networks (circuits) ; Asia-Pacific ; Circuit designs ; CMOS circuits ; EDP contour ; Energy-delay product ; Low power design ; Low powers ; New model ; Transistor sizing ; Integrated circuit manufacture
  8. Source: APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 4 December 2006 through 6 December 2006 ; 2006 , Pages 1394-1398 ; 1424403871 (ISBN); 9781424403875 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4145661