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System-Level Policies to Reduce Power Consumption in Fault-Tolerant Embedded Systems

Ansari, Mohsen | 2021

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 54391 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ejlali, Alireza
  7. Abstract:
  8. Technology scaling allows integrating multiple cores onto a single chip to make the mainstream for advanced embedded systems. However, technology scaling results in aggravating the reliability problem of on-chip systems because of increasing transient fault rate due to lower voltages and shrinking transistor dimensions that lead to smaller critical charges. Multicore systems provide a great opportunity to implement reliability mechanisms such as redundant multithreading (RMT) and process level redundancy. Task replication (e.g., RMT) is a well-established technique to achieve high reliability against transient faults. However, replicated executions may increase power consumption beyond the chip Thermal Design Power (TDP) constraint. TDP is considered as the highest sustainable power that a chip can dissipate before being forced to exploit a performance throttling mechanism, e.g., Dynamic Thermal Management (DTM). If a chip violates its TDP, it automatically restarts or significantly reduces its performance to prevent a permanent damage. Therefore, due to the unwanted system restarts, DTM techniques may not be applicable for the systems that require satisfying strict timing constraints. In this dessertation, at first, we illustrate how fault-tolerance techniques may increase peak power consumption and consequently may result in a chip TDP violation. Then, we propose a peak-power-aware scheduler that manages peak power consumption for different task models on multicore embedded systems. The scheduler schedules different applications on different types of cores in two types of multicore platforms without violating timing constraints. The proposed methods aim at removing overlaps of the peak power of concurrently executing tasks to keep the power consumption below the chip TDP. To do this, considering the tasks’ power profiles, at first, we partition the tasks into parts with different peak power values. Then, based on the task models, we propose policies for scheduling the partitioned tasks. In this dissertation, we have proposed five policies to schedule applications of embedded systems such that the power consumption is kept below the power constraints. These policies are: (i) the Peak-Power-Aware Longest Task First (PPA-LTF) policy for scheduling the task graph model, (ii) the Maximum-Peak-Power-First (MPPF) and Maximum-Peak-Power-Last (MPPL) policies for scheduling the frame-based task model, (iii) the Peak-Power-Aware Earliest-Deadline-First (PPA-EDF) and Peak-Power-Aware Earliest-Deadline-Late (PPA-EDL) policies for scheduling the periodic tasks. In summary, our proposed schemes try to spread out the parts of tasks that consume high power over the entire interval before the deadline with the aim of keeping the total peak power below the chip TDP
  9. Keywords:
  10. Peak Power Consumption ; Embedded System ; Fault Tolerance ; Replication Data ; Thermal Design Power

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