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A low-power, multichannel gated oscillator-based CDR for short-haul applications

Tajalli, A ; Sharif University of Technology | 2005

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  1. Type of Document: Article
  2. DOI: 10.1109/lpe.2005.195496
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2005
  4. Abstract:
  5. A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51mW/Channel/Gbps while occupies 0.045mm2 silicon area. Copyright 2005 ACM
  6. Keywords:
  7. Bit error rate ; Data acquisition ; Electric currents ; Electric potential ; Gates (transistor) ; Jitter ; Power electronics ; Clock and data recovery (CDR) system ; Digital CMOS ; Frequency offsets ; Jitter tolerance ; Oscillators (electronic)
  8. Source: 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, 8 August 2005 through 10 August 2005 ; 2005 , Pages 107-110 ; 15334678 (ISSN)
  9. URL: https://dl.acm.org/doi/10.1145/1077603.1077631