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Experimental evaluation of Master/Checker architecture using power supply- and software-based fault injection

Rajabzadeh, A ; Sharif University of Technology | 2004

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  1. Type of Document: Article
  2. DOI: 10.1109/OLT.2004.1319694
  3. Publisher: 2004
  4. Abstract:
  5. This paper presents an experimental evaluation of the effectiveness of the Master/Checker (M/C) architecture in a 32-bit Pentium® processor system using both power-supply disturbance (PSD) fault injection and software-implemented fault injection (SWIFI) methods. A total of 6000 faults were injected in the Master processor to measure the error detection coverage of the Checker processor. The results of the experiments with PSD fault injection show that the error detection coverage of the M/C architecture is about 66.13%, which is not quite effective. This low coverage depends on the high rate of Master processor hangs because of voltage fluctuation. The coverage increased to about 99.73% when an external watchdog was combined with the M/C architecture. In the case of SWIFI, the results show that the M/C architecture has reasonable outcome and is capable of detecting about 100% of the errors
  6. Keywords:
  7. Power supplies ; Safety ; Embedded system ; Voltage fluctuations ; Process design ; Redundancy ; Hardware ; Pins ; Application specific integrated circuits ; Fault detection
  8. Source: Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004, Madeira Island, 12 July 2004 through 14 July 2004 ; 2004 , Pages 239-244 ; 0769521800 (ISBN); 9780769521800 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/1319694