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Multiple upsets tolerance in SRAM memory
109 viewed

Multiple upsets tolerance in SRAM memory

Argyrides, C

Multiple upsets tolerance in SRAM memory

Argyrides, C ; Sharif University of Technology | 2007

109 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/iscas.2007.378465
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2007
  4. Abstract:
  5. This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these methods in terms of fault detection and correction of multiple faults regarding to the area overhead. © 2007 IEEE
  6. Keywords:
  7. Codes (symbols) ; Fault detection ; Fault tolerance ; Hamming codes ; Reed Muller codes ; Static random access storage
  8. Source: 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 365-368 ; 02714310 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/4252647