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    Smooth projective hash function from codes and its applications

    , Article IEEE Transactions on Services Computing ; 2021 ; 19391374 (ISSN) Koochakshooshtari, M ; Aref, M. R ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    Nowadays, Smooth Projective Hash Functions (SPHFs) play an important role in constructing cryptographic tools such as secure Password-based Authenticated Key Exchange (PAKE) protocol in the standard model, oblivious transfer, and zero-knowledge proofs. Specifically, in this paper, we focus on constructing PAKE protocol; that is, a kind of key exchange protocol which needs only a low entropy password to produce a cryptographically strong shared session key. In spite of relatively good progress of SPHFs in applications, it seems there has been little effort to build them upon quantum-resistant assumptions such as lattice-based cryptography and code-based cryptography to make them secure... 

    STAIR: high reliable STT-MRAM aware multi-level I/O cache architecture by adaptive ECC allocation

    , Article 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, 9 March 2020 through 13 March 2020 ; 2020 , Pages 1484-1489 Hadizadeh, M ; Cheshmikhani, E ; Asadi, H ; ACM Special Interest Group on Design Automation (SIGDA); et al.; European Design and Automation Association (EDAA); European Electronic Chips and Systems Design Initiative (ECSI); IEEE Council on Electronic Design Automation (CEDA); SEMI Strategic Technology Community and Electronic System Design Alliance (ESD Alliance) ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Hybrid Multi-Level Cache Architectures (HCAs) are promising solutions for the growing need of high-performance and cost-efficient data storage systems. HCAs employ a high endurable memory as the first-level cache and a Solid-State Drive (SSD) as the second-level cache. Spin-Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising candidates for the first-level cache of HCAs because of its high endurance and DRAM-comparable performance along with non-volatility. However, STT-MRAM faces with three major reliability challenges named Read Disturbance, Write Failure, and Retention Failure. To provide a reliable HCA, the reliability challenges of STT-MRAM should be carefully addressed.... 

    PKC-PC: A variant of the McEliece public-key cryptosystem based on polar codes

    , Article IET Communications ; Volume 14, Issue 12 , 2020 , Pages 1883-1893 Hooshmand, R ; Koochak Shooshtari, M ; Aref, M. R ; Sharif University of Technology
    Institution of Engineering and Technology  2020
    Abstract
    Polar codes are novel and efficient error-correcting codes with low encoding and decoding complexities. These codes have a channel-dependent generator matrix, which is determined by the code dimension, code length and transmission channel parameters. A variant of the McEliece public-key cryptosystem based on polar codes, called the PKC-PC, is studied. Since the structure of the polar codes' generator matrix depends on the parameters of the channel, the authors have used an efficient approach to conceal their generator matrix. The proposed approach is based on a random selection of rows of the matrix by which a random generator matrix is constructed. Using the characteristics of polar codes... 

    AWARE: Adaptive way allocation for reconfigurable ECCs to protect write errors in STT-RAM caches

    , Article IEEE Transactions on Emerging Topics in Computing ; Volume 7, Issue 3 , 2019 , Pages 481-492 ; 21686750 (ISSN) Azad, Z ; Farbeh, H ; Hosseini Monazzah, A. M ; Miremadi, S. G ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

    Enhancing Reliability of STT-MRAM Caches by Eliminating Read Disturbance Accumulation

    , Article 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019, 25 March 2019 through 29 March 2019 ; Pages 854-859 , 2019 , Pages 854-859 ; 9783981926323 (ISBN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; ACM Special Interest Group on Design Automation (SIGDA); Electronic System Design (ESD) Alliance; et al.; European Design and Automation Association (EDAA); European Electronic Chips and Systems Design Initiative (ECSI); IEEE Council on Electronic Design Automation (CEDA) ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-Transfer Torque Magnetic RAM (STT-MRAM) as one of the most promising replacements for SRAMs in on-chip cache memories benefits from higher density and scalability, near-zero leakage power, and non-volatility, but its reliability is threatened by high read disturbance error rate. Error-Correcting Codes (ECCs) are conventionally suggested to overcome the read disturbance errors in STT-MRAM caches. By employing aggressive ECCs and checking out a cache block on every read access, a high level of cache reliability is achieved. However, to minimize the cache access time in modern processors, all blocks in the target cache set are simultaneously read in parallel for tags comparison operation... 

    Robin: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches

    , Article Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 21 January 2019 through 24 January 2019 ; 2019 , Pages 173-178 ; 9781450360074 (ISBN) Cheshmikhani, E ; Farbeh, H ; Asadi, H ; ACM SIGDA; Cadence Design Systems, Inc.; CEDA; EIC; IEEE CAS; IPSJ ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a promising alternative for SRAMs in on-chip cache memories. Besides all its advantages, high error rate in STT-MRAM is a major limiting factor for on-chip cache memories. In this paper, we first present a comprehensive analysis that reveals that the conventional Error-Correcting Codes (ECCs) lose their efficiency due to data-dependent error patterns, and then propose an efficient ECC configuration, so-called ROBIN, to improve the correction capability. The evaluations show that the inefficiency of conventional ECC increases the cache error rate by an average of 151.7% while ROBIN reduces this value by more than 28.6x. © 2019 Association for... 

    ORIENT: organized interleaved ECCs for new STT-MRAM caches

    , Article Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 ; Volume 2018-January , 19 April , 2018 , Pages 1187-1190 ; 9783981926316 (ISBN) Azad, Z ; Farbeh, H ; Hosseini Monazzah, A. M ; Sharif University of technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations... 

    Optimal quantum error correcting codes from absolutely maximally entangled states

    , Article Journal of Physics A: Mathematical and Theoretical ; Volume 51, Issue 7 , 2018 ; 17518113 (ISSN) Raissi, Z ; Gogolin, C ; Riera, A ; Acin, A ; Sharif University of Technology
    Institute of Physics Publishing  2018
    Abstract
    Absolutely maximally entangled (AME) states are pure multi-partite generalizations of the bipartite maximally entangled states with the property that all reduced states of at most half the system size are in the maximally mixed state. AME states are of interest for multipartite teleportation and quantum secret sharing and have recently found new applications in the context of high-energy physics in toy models realizing the AdS/CFT-correspondence. We work out in detail the connection between AME states of minimal support and classical maximum distance separable (MDS) error correcting codes and, in particular, provide explicit closed form expressions for AME states of n parties with local... 

    An efficient Protection Technique for last level STT-RAM caches in multi-core processors

    , Article IEEE Transactions on Parallel and Distributed Systems ; Volume 28, Issue 6 , 2017 , Pages 1564-1577 ; 10459219 (ISSN) Azad, Z ; Farbeh, H ; Hosseini Monazzah, A. M ; Miremadi, S. G ; Sharif University of Technology
    IEEE Computer Society  2017
    Abstract
    Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAMseems to be themost promising alternative.With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches.High probability of write error due to stochastic switching is amajor problemin STT-RAMs. Conventional Error-CorrectingCodes (ECCs) impose significant area and energy consumption overheads to protect STT-RAMcaches. These overheads in multi-core processors with... 

    AWARE: Adaptive way allocation for reconfigurable ECCs to protect write errors in STT-RAM caches

    , Article IEEE Transactions on Emerging Topics in Computing ; 2017 ; 21686750 (ISSN) Azad, Z ; Farbeh, H ; Hosseini Monazzah, A. M ; Miremadi, S. G ; Sharif University of Technology
    IEEE Computer Society  2017
    Abstract
    Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

    Floating-ECC: dynamic repositioning of error correcting code bits for extending the lifetime of STT-RAM caches

    , Article IEEE Transactions on Computers ; Volume 65, Issue 12 , 2016 , Pages 3661-3675 ; 00189340 (ISSN) Farbeh, H ; Kim, H ; Miremadi, S. G ; Kim, S ; Sharif University of Technology
    IEEE Computer Society  2016
    Abstract
    Spin-Transfer Torque RAM (STT-RAM) is a promising alternative to SRAM for implementing on-chip L2 and L3 caches. One of the most critical challenges in STT-RAM is reliability due to limited write endurance, which results in insufficient lifetime, as well as various types of errors. Previous studies have focused on either presenting various cache architectures/management techniques to improve the lifetime of STT-RAM caches or utilizing different Error Correcting Codes (ECCs) to protect against the permanent and transient errors. However, there is no quantitative analysis in the literature to determine the impact of ECCs on the lifetime of the STT-RAM caches. This paper formulates this impact... 

    A new blind energy based DWT-SVD domain watermarking using error control coding

    , Article International Journal of Knowledge-Based and Intelligent Engineering Systems ; Volume 19, Issue 2 , 2015 , Pages 135-141 ; 13272314 (ISSN) Tahzibi, M ; Sahebjamiyan, M ; Shahbahrami, A ; Sharif University of Technology
    IOS Press  2015
    Abstract
    The growth of data communication networks has made digital watermarking an important issue for copyright and content protection. Achieving high level of robustness and good transparency are the main objectives of developing every digital watermarking algorithm. From among transform domains as the basis of watermark hiding place, Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT) and Singular Value Decomposition (SVD) are the most commonly used transforms in literature. In this paper we propose a new hybrid DWT-SVD domain watermarking scheme taking into account the energy content of every chosen block of the selected DWT sub-band coefficients. Before embedding, we append a... 

    FTSPM: A fault-tolerant scratchpad memory

    , Article Proceedings of the International Conference on Dependable Systems and Networks ; 2013 , Page(s): 1 - 10 ; 9781467364713 (ISBN) Monazzah, A. M. H ; Farbeh, H ; Miremadi, S. G ; Fazeli, M ; Asadi, H ; Sharif University of Technology
    2013
    Abstract
    Scratch Pad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability... 

    A new TH-CDMA scheme for dispersive infrared channel and its performance evaluation

    , Article Journal of Optical Communications ; Volume 32, Issue 1 , 2011 , Pages 21-36 ; 01734911 (ISSN) Hamdi, M ; Nasiri Kenari, M ; Sharif University of Technology
    2011
    Abstract
    Infrared indoor wireless communications using nondirected links are subject to severe multipath distortion which causes intersymbol interference (ISI). To lessen multipath distortion effect and thereby to improve the system performance, in this paper, we consider a new time-hopping based multiple access scheme for this channel, in which one pulse is transmitted in each bit interval. The position of the pulse is determined based on the output of a low rate error correcting code along with the user's dedicated PN code. We evaluate the multiple access performance of the system for correlation receiver considering background noise, dark current, and thermal noise. We compare the performance of... 

    An internally coded TH/OCDMA scheme for fiber optic communication systems and its performance analysis - Part II: Using frame time hopping code

    , Article IEEE Transactions on Communications ; Volume 57, Issue 1 , 2009 , Pages 50-55 ; 00906778 (ISSN) Karimi, M ; Nasiri Kenari, M ; Sharif University of Technology
    2009
    Abstract
    In Part I, a new internally coded time hoping optical code division multiple access (TH/OCDMA) scheme for fiber optic communication systems has been proposed and its multiple access performance has been evaluated using optical orthogonal code (OOC). Due to low cardinality of OOCs with a correlation value of 1, the capability of the proposed scheme could not be utilized effectively for an increasing number of simultaneous users. In this part, we consider applying the internally coded technique introduced in part one to the frame time hopping/OCDMA scheme. We evaluate the multiple access performance of the system for the three detectors introduced in Part I. Our results demonstrate the... 

    Inflating compressed samples: a joint source-channel coding approach for noise-resistant compressed sensing

    , Article 2009 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2009, Taipei, 19 April 2009 through 24 April 2009 ; 2009 , Pages 2957-2960 ; 15206149 (ISSN); 9781424423545 (ISBN) HesamMohseni, A ; Babaie Zadeh, M ; Jutten, C ; Institute of Electrical and Electronics Engineers; Signal Processing Society ; Sharif University of Technology
    2009
    Abstract
    Recently, a lot of research has been done on compressed sensing, capturing compressible signals using random linear projections to a space of radically lower dimension than the ambient dimension of the signal. The main impetus of this is that the radically dimension-lowering linear projection step can be done totally in analog hardware, in some cases even in constant time, to avoid the bottleneck in sensing and quantization steps where a large number of samples need to be sensed and quantized in short order, mandating the use of a large number of fast expensive sensors and A/D converters. Reconstruction algorithms from these projections have been found that come within distortion levels... 

    Multiple-access performance analysis of combined time-hopping and spread-time CDMA system in the presence of narrowband interference

    , Article IEEE Transactions on Vehicular Technology ; Volume 58, Issue 3 , 2009 , Pages 1315-1328 ; 00189545 (ISSN) Shayesteh, M. G ; Nasiri Kenari, M ; Sharif University of Technology
    2009
    Abstract
    We consider a combined time-hopping (TH) and spread-time (ST) multiple-access technique that uses an internal code. In this method, the duration of each bit is divided into Ns frames. The outputs of the encoder and a pseudorandom (PN) sequence specify the number of the frame in which the data bit is transmitted in ST code-division multiple-access (ST-CDMA) form using the second PN sequence. We consider the correlator receiver, followed by the channel decoder. We obtain the performance of the combined method in additive white Gaussian noise (AWGN) and fading channels in the presence of multiple-access interference (MAI) and narrowband interference (NBI). We also consider the conventional... 

    Decoding real-field codes by an iterative expectation-maximization (EM) algorithm

    , Article 2008 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP, Las Vegas, NV, 31 March 2008 through 4 April 2008 ; 2008 , Pages 3169-3172 ; 15206149 (ISSN) ; 1424414849 (ISBN); 9781424414840 (ISBN) Zayyani, H ; Babaie Zadeh, M ; Jutten, C ; Sharif University of Technology
    2008
    Abstract
    In this paper, a new approach for decoding real-field codes based on finding sparse solutions of underdetermined linear systems is proposed. This algorithm iteratively estimates the positions and the amplitudes of the sparse errors (or noise impulses) using an Expectation-Maximization (EM) algorithm. Iterative estimation of amplitudes is done in the Expectation step (E-step), while iterative estimation of error positions is done in the Maximization step (M-step). Simulation results show 1-2 dB improvement over Linear Programming (LP) which has been previously used for error correction. ©2008 IEEE  

    A Lagrange interpolation based error correction coding for the images

    , Article ISPA 2007 - 5th International Symposium on Image and Signal Processing and Analysis, Istanbul, 27 September 2007 through 29 September 2007 ; 2007 , Pages 293-298 ; 9789531841160 (ISBN) Ajorloo, H ; Manzuri Shalmani, M. T ; Lakdashti, A ; Sharif University of Technology
    2007
    Abstract
    An extended version of Lagrange interpolation is developed for coding of images in real field in a way that at the receiver, one can restore the lost portions of the images. The proposed solution is similar to channel coding techniques, but it is done before source coding at the transmitter and after decoding of the compressed data at the receiver. Our proposed solution is faster than the other one reported in the literature when the size of damaged blocks is large  

    Reliable video transmission using codes close to the channel capacity

    , Article IEEE Transactions on Circuits and Systems for Video Technology ; Volume 16, Issue 12 , 2006 , Pages 1550-1556 ; 10518215 (ISSN) Dianat, R ; Marvasti, F ; Ghanbari, M ; Sharif University of Technology
    2006
    Abstract
    Long Reed-Solomon codes over the prime field GF(216 + 1) are proposed as a low overhead channel code for reliable transmission of video over noisy and lossy channels. The added redundancy is near optimal from the information theoretic point of view contrary to the conventionally used intra-coding and sync (marker) insertion in video transmission that are not justified theoretically. Compared to known source-channel coding methods, we have achieved the quality of the output of source coder by providing nearly error free transmission. (By nearly error free we mean an arbitrarily small error probability.) The price paid for such remarkable video quality improvement and relatively low complexity...