Sharif Digital Repository

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of... 

Due to the rapid growth of technology, the number of cores on a single chip has increased, caused thousands (or millions) of transistors being tight in a new layout consequently. Technology scaling arise the sensitivity and likelihood of faults. Thus, fault management is one of the important challenging issues in multiple core design we should face. Faults can be permanent, transient, and intermittent. Apart from the fact that how and when a fault occurs, supporting a fault-tolerant or fault-prevention routing is a must in NoCs. To target mentioned problem, we have proposed two routing algorithm in this thesis. The first algorithm is FaulToleReR, which is a reconfigurable fault (faults can... 

Deep Neural Networks (DNNs) are widely used as a promising machine learning method in different applications and come with intensive computation and storage requirements. In recent years, several pieces of prior work have proposed different accelerators to improve DNNs processing. We observe that although the state-of-the-art DNN accelerators effectively process some network layers of certain shapes, they fail to keep computation resources fully utilized for many other layers. The reason is twofold: first, the mapping algorithm is unable to employ all compute cores for processing some layer types and dimension sizes, and second, the hardware cannot perform data distribution and aggregation... 

Advance in VLSI integration level has realized multi-core system-on-chip. For inter-IP communication on-chip network is proposed as a substitute for simple interconnects such as bus fabrics and expensive point-to-point links. Although onchip networks have some superiorities over simple interconnects, but they need more of real estate resource. Although buses are not scalable, they are still popular for their simple communication mechanism. There are so many proposed mechanisms to make buses more scalable and more popular. Most of them try to change bus structure by segmenting and using reconfigurable methods. In this thesis, we explore buses delay by considering the number of component in a... 

Combination of 3D stacking and network-on-chip (NoC), known as 3D NoC, has some advantages such as reduced propagation delay, chip area and interconnect, and power consumption, and bandwidth increase. Despite these advantages, the increased power density per chip area due to area decrease causes thermal problems in 3D NoCs to be more critical than 2D NoCs. Therefore, design of temperature management algorithms is essential for these systems. One of the dynamic thermal management techniques is task migration that balances generated thermal among cores.In this thesis, we propose a task migration scheme using feedback control for 3D NoCs. The main purpose of this scheme is to decrease the peak... 

With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Power-gating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overheads of the packets that encounter powered-off... 

NOCs contribute to a large portion of a many-core SOC power consumption. A significant fraction of the mentioned power consumption is due to the buffers, crossbar and the links. Thus, in this thesis, a new method would be introduced which reduces the power consumption of the NOCs in large scale. This method utilizes the latency asymmetry of router pipeline stages for dynamic power reduction and uses different voltage swings for buffers, links and the crossbar in order to decrease the dynamic power consumption while maintaining the performance. Moreover, since the static power consumption has gained a noticeable importance in recent years, a method for degrading this power component is also... 

The fast development of semiconductor industry has moved the design methodology to SoC (System on Chip) design. This growing trend has made it possible to perform parallel processing on a chip. Due to the increasing number of processing elements In SoCs, buses become the bottleneck of the system and lead to non-efficient designs. In the early years of the current decade, Network on Chip (NoC) was introduced and considered by the researchers. NoC is an efficient solution that eliminates bus bottleneck and it had been introduced as a suitable substructure for interconnecting processing elements. The NoCs were originally built based on Interconnection Networks. Although initially aimed at... 

Recent advances in VLSI technology have led to integrate a few billion transistors on a chip. Systems on Chip provide solutions to the design problems of these systems. As technology scales down to deep sub-micron dimensions, the delay and power consumption of global interconnects become the major bottleneck in SoC design. Networks on Chip (NoCs) have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in large VLSI design. The market trend to mobile digital systems and battery-powered devices add power as a new dimension to VLSI design space in addition to speed and area. Interconnect wires dissipate a significant fraction of power... 

With progress in integrated circuits technology, on chip systems have become operational, and after that, onchip network are as solutions to improve onchip connections and also its scalability. With improving technology, the number of cores on chips can be more, that it causes increasing importance of produced problems by parallel links. Serial links are one of the methods to decrease these problems. Serial links have some advantages in compare with parallel links in some aspects like: clock pulse skew, cross talk, area cost, difficulties in wiring and synchronizing clock pulse signals. But any way, problems such as high operational frequency and complicated serializer and deserializer... 

The fast development of semiconductor industry has moved the design methodology to SoC (System on Chip) design. Due to the increasing number of processing elements, In SoC, buses become the bottleneck of the system and lead to non-efficient designs. NoC (Network onChip) is an efficient solution that eliminates bus bottleneck and it had been introduced as a suitable substructure for interconnecting processing elements. The NoCs were originally built based on Interconnection Networks.They have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in any large SoC design. The trend of market to mobile digital systems and battery-powered devices,... 

Recent advances in VLSI technologies have enabled current silicon dies to accommodate billions of transistors in the design of very complex System-on-Chips (SoCs). To address the resulting complexity, Network-on-Chips (NoCs) have emerged as a paradigm to design scalable communication architecture to connect the processing cores of an SoC. However, smaller feature sizes, lower voltage levels and higher frequencies in Deep Sub-Micron (DSM) technologies make NoCs highly susceptible to transient faults, e.g., crosstalks, particle strikes, electro-magnetic interferences, and power supply disturbances. Single Event Upsets (SEUs) caused by high energy particle strikes as well as crosstalks are the... 

In this thesis, we propose a processor allocation mechanism for run-time assignment of a set of communicating tasks of input applications onto the processing nodes of a Chip Multiprocessor (CMP), when the arrival order and execution life-time of the input applications are not known a priori. This mechanism targets the on-chip communication and aims to reduce the power and latency of the Network-on-Chip (NoC). In this work, we benefit from the advantages of non-contiguous processor allocation mechanisms, by allowing the tasks of the input application to be mapped onto disjoint regions (sub-meshes) and then virtually connecting them by bypassing the router pipeline stages of inter-region... 

With increasing number of processors on a chip, the role of interconnections becomes more important in both power consumption and bandwidth. As a result, in MultiProcessor System-on-Chip architectures, the design constraints will shift from "Computational Constraints" to "Communicational Constraints". Nowadays, optical information transfer is introduced as a suitable substitution for electrical interconnections in chips, which can eliminate their problems. Many different optical networks have been presented so far. These networks can be divided into two subcategories. Networks of the first category use an electrical infrastructure as well as optical one. Hence, the scalability of scheme is... 

Three dimensional or vertical integration is a new way of increasing the performance and expanding the capacities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. 3D Networks on chip have a lot of benefits such as capability of large scale integration, increasing the density of elements on chip and expanding the dimensions of chips. Large scale integration and increasing density of elements will cause more consumption of energy. This more energy consumption will cause high temperature in chips. Although high temperature has been managed in 2D networks, but necessity of... 

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. This concept is the basis of the Dark Silicon definition. To address this issue, it is needed a structure to guaranty Limited power budget and obtain sufficient flexibility and performance for different applications with variety communication needs. Regarding to this structure, our aim is to present a platform for Networks-on-Chip that uses clustering and resource sharing among cores. Moreover, as task mapping on processing elements in NOCs is one of the most effective way to... 

Combination of 3D IC technology and network on chip (NoC) is an effective solution to increase system scalability, and also alleviate the interconnect problem in large scale integrated circuits. However, due to the increased power density in 3D NoC systems and the destructive impact of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. Since hardware thermal control techniques, such as DVFS, can cause significant degradation on chip performance, in this thesis we propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in 3D NoCs. The objective of this... 

Recent advances in Very-Large-Scale Integration (VLSI) technologies have enabled designers to integrate a large number of Processing Elements (PEs) on a single die. According to International Technology Roadmap for Semiconductors (ITRS), the number of PEs will reach 5000 on a single die in 2021. Although the main achievements of such rapid advancement in chips are high processing speed, shrinkage of technology size has made chips highly sensitive to different challenges. Networks on chip (NoCs), as an example of these systems, are not exempted from these challenges. Crosstalk fault is one of the major fault resources in NoCs. Crosstalk faults occur due to coupling capacitances between... 

In past decades, we have seen the rise of integration density in chips making it possible to design a whole system on a single chip. The previously designed interconnection architectures for multiprocessors systems cannot directly be applied in on-chip systems (especially when the number of processor elements increases) since they require a different type of a cost-performance trade-off. This is why the interconnection networks of systems-on-chip (SoC) are such a problem. Network-on-chip (NoC) was being proposed as a scalable and reusable communication platform for SoCs, which makes use of the network model to develop efficient on-chip communication infrastructures. The NoC has a layered and... 

Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantage of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the ITRS annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the operating frequency of RF devices increases,...