Sharif Digital Repository

This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU).... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

This paper presents a modified astrocyte model that allows a convenient digital implementation. This model is aimed at reproducing relevant biological astrocyte behaviors, which provide appropriate feedback control in regulating neuronal activities in the central nervous system. Accordingly, we investigate the feasibility of a digital implementation for a single astrocyte and a biological neuronal network model constructed by connecting two limit-cycle Hopf oscillators to an implementation of the proposed astrocyte model using oscillator-astrocyte interactions with weak coupling. Hardware synthesis, physical implementation on field-programmable gate array, and theoretical analysis confirm... 

In this paper we investigate the modulation properties of high frequency EEG activities by delta waves during various depth of anesthesia. We show that slow and fast delta waves (0-2 Hz and 2-4 Hz respectively) and high frequency components of the EEG (8-20 Hz) are correlated with each other and there is a kind of phase locking between them that varies with depth of anesthesia. Our analyses show that maximum amplitudes of high frequency components of the EEG signal are appeared in different phases of slow and fast delta waves when the concentration of Desflurane and Propofol anesthetic agents varies in a patient. There are some slight differences in using slow and fast components of delta... 

Continuous clocks, i.e., clocks that measure time in a continuous manner, are regarded as an essential component of sensing technology. Precision and recurrence time are two basic features of continuous clocks. In this paper, in the framework of quantum estimation theory various models for continuous quantum clocks are proposed, and all tools of quantum estimation theory are employed to seek the characteristics of clocks with high precision and long recurrence time. Then, in a resource-based approach, the performances of the proposed models are compared. It is shown that quantum clocks based on an n two-qubit system not only can have better precision than quantum clocks based on a 2n... 

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the... 

Slow-gamma (35-45 Hz) phase synchronization and the coupling between slow-gamma and low-frequency theta oscillations (4–8 Hz) are closely related to memory retrieval and cognitive functions. In this pilot study, we assess the Phase Amplitude Coupling (PAC) between theta and slow-gamma oscillatory bands and the quality of synchronization in slow-gamma oscillations using Phase Locking Value (PLV) on EEG data from healthy individuals and patients diagnosed with amnestic Mild Cognitive Impairment (aMCI) and Alzheimer's Disease (AD) during an oddball olfactory task. Our study indicates noticeable differences between the PLV and PAC values corresponding to olfactory stimulation in the three groups... 

Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between... 

A very low power CMOS, 1.5V, 2.5GHz prescaler was designed. Implemented in 0.25u standard CMOS technology, this prescaler can operate up to 3GHz range. The prescaler consists of three delay flip flops (DFF) that work synchronously with RF sinusoidal clock and divides by 4 or 5 according to control signal  

This paper introduces a Dynamic Read SRAM (DRSRAM) architecture for high-density subthreshold RAM applications. DRSRAM performs a dynamic read operation to overcome the poor stability and bitline leakage problem of 6T SRAM cell in sub-threshold region. It is shown that there is fundamental limit for wordline activation time and recovery time under a given cell mismatch and bitline leakage. To verify the proposed technique, a 64128 bit array of the 6T bit-cell is simulated in 90 nm CMOS technology. The simulation results show a 100% noise margin enhancement at subthreshold region. This design operates down to 300 mV at a 1 MHz clock rate with noise margins as large as 72 mV. This design... 

This paper assesses message missing failures in a FlexRay-based network. The assessment is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller; the parts are: controller host interface, protocol operation control, coding and decoding unit, media access control and clock synchronization process. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. This HDL model of the controller is exploited to setup a FlexRay-based network composed of four nodes. The results of fault injection show that about 35% of faults led to the message missing failures. The controller host interface and the clock... 

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 μm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of... 

This paper presents several efficient architectures of dynamic/static edge-triggered flip-flops with a compact embedded logic. The proposed structure, which benefits from the overlap period, fixes most of the drawbacks of the dynamic logic family. The design issues of setting the appropriate overlap period for this architecture are explained. The proposed overlap-based approach is compared with several state-of-the-art dynamic/static logic styles in implementing a 4-bit shift register and an odd-even sort coprocessor using different CMOS technologies. The simulation results showed that the overlap-based logic cells become much more efficient when the complexity of their embedded logic... 

This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is... 

RSA based SmartCards have been widely used in security services such as secure data transmission in many applications over the past few years. Generation of a secure key pair which is based on finding a pair of large prime numbers is an indispensable part of creating a secure channel. This paper describes a novel approach for secure and fast key generation of the public key cryptographic algorithm of RSA. This method has been implemented on a typical SmartCard equipped with a crypto-coprocessor and a true random number generator. An efficient method for generating the large random prime numbers is proposed that considerably reduces the total time required for generating a key pair. The key... 

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is... 

A high-Q, tunable, bandpass filtered amplifier structure is proposed which is based on a novel Q enhancement technique in N-path filters. Using Fourier series analysis, frequency response of an N-path filter as well as the aliasing effects which are present in it are derived. Frequency translation of unwanted contents at higher frequencies to the center frequency of the bandpass filter is called harmonic fold back (HFB). It is shown that using an additional N-path filter with the same clock frequency but different clock phases can reduce the HFB. The required conditions for fold back elimination are derived fromFourier series expansion analysis. In order to achieve HFB reduction as well as... 

A5/1 is the strong version of the encryption algorithm on GSM (Global System for Mobile communications) used in many countries. It is constructed of a combination of three LFSRs (Linear Feedback Shift Registers) with irregular clocking manner. One of the most practical attacks against this algorithm is time-memory trade-off attack, which is based on birthday paradox. The goal of this attack is to find any intersection between precomputed LFSRs states set and set of states generating the output bits in the actual execution of the algorithm. In order to increase feasibility of this attack, the biased birthday attack was introduced. In this attack special states producing a specific pattern in... 

By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents an improved scheme for generating pre-computed test patterns in core-based systems on chip. This approach reduces the number of pre-computed test patterns and as the result, test application time (TAT) will be decreased....