Loading...

DuCNoC: a high-throughput FPGA-based NoC simulator using dual-clock lightweight router micro-architecture

Mardani Kamali, H ; Sharif University of Technology | 2018

1017 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/TC.2017.2735399
  3. Publisher: IEEE Computer Society , 2018
  4. Abstract:
  5. On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM. Additionally, we implement a two-layer configurable global interconnection in our proposed architecture to (1) reduce virtualization time overhead, (2) make an efficient trade-off between the resource utilization and simulation time of the whole simulator, and especially (3) provide the capability of simulating irregular topologies. Migration of some important sub-modules like traffic generators (TGs) and traffic receptors (TRs) to software side, and implementing a dual-clock context switching in virtualization are other major features of DuCNoC. Thanks to its dual-clock router micro-architecture, as well as TGs and TRs migration to software side, DuCNoC can simulate a 100-node (10 × 10) non-virtualized or a 2048-node virtualized mesh network on Xilinx Zynq-7000. © 2017 IEEE
  6. Keywords:
  7. Dual-clock ; FPGA ; Router micro-architecture ; Clocks ; Computer architecture ; Computer software ; Distributed computer systems ; Economic and social effects ; Field programmable gate arrays (FPGA) ; Integrated circuit interconnects ; Interconnection networks (circuit switching) ; Network architecture ; Network-on-chip ; Routers ; Simulators ; System-on-chip ; Topology ; Virtual reality ; Virtualization ; Design space exploration ; Global interconnection ; Irregular topology ; Micro architectures ; Multiprocessor interconnections ; On-chip interconnection ; Proposed architectures ; Resource utilizations ; Integrated circuit design
  8. Source: IEEE Transactions on Computers ; Volume 67, Issue 2 , February , 2018 , Pages 208-221 ; 00189340 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8000664