Sharif Digital Repository

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The... 

Long and continuous running of software can cause software aging-induced errors and failures. Cloud data centers suffer from these kinds of failures when Virtual Machine Monitors (VMMs), which control the execution of Virtual Machines (VMs), age. Software rejuvenation is a proactive fault management technique that can prevent the occurrence of future failures by terminating VMMs, cleaning up their internal states, and restarting them. However, the appropriate time and type of VMM rejuvenation can affect performance, availability, and power consumption of a system. In this paper, an analytical model is proposed based on Stochastic Activity Networks for performance evaluation of... 

In this paper, Stochastic Activity Networks (SANs) are used to model and evaluate the performance and power consumption of an Infrastructure-as-a-Service (IaaS) cloud. The proposed SAN model is scalable and flexible, yet encompasses some details of an IaaS cloud, such as Virtual Machine (VM) provisioning, VM multiplexing, and failure/repair behavior of VMs. Using the proposed SAN, a power-aware self-adaptive resource management scheme is presented for IaaS clouds that automatically adjusts the number of powered-on Physical Machines (PMs) regarding variable workloads in different time intervals. The proposed scheme respects user-oriented metrics by avoiding Service Level Agreement (SLA)... 

Multicore platforms provide great opportunity for implementation of fault-tolerance techniques to achieve high reliability in real-time embedded systems. Passive redundancy is well-suited for multicore platforms and a well-established technique to tolerate transient and permanent faults. However, it incurs significant power overheads, which go wasted in fault-free execution scenarios. Meanwhile, due to the Thermal Design Power (TDP) constraint, in some cases it is not feasible to simultaneously power on all cores on a multicore platform. Since TDP is the maximum sustainable power that a chip can consume, violating TDP makes some cores automatically restart or significantly reduce their... 

With the widespread use of Internet of Things (IoT) in every aspect of human's daily life, communications of such an enormous amount of existing embedded devices in these systems arise many new challenges from power consumption, performance, and reliability perspectives. Communications in an IoT infrastructure are managed by a set of policies which are determined by Objective Functions (OFs). Thus, OFs are the most important contributors in facing with the mentioned challenges. In this paper, due to the lack of information on how OFs affect the primary properties of an IoT infrastructure, we have compared three well-known OFs (OF0, MRHOF, and OFFL) from power consumption, performance, and... 

We propose an energy-efficient procedure for transponder configuration in few-mode fiber-based elastic optical networks in which bit error rate and physical constraints are guaranteed and joint optimization of temporal, spectral, and spatial resources are addressed. We use geometric convexification techniques to provide convex formulations for the signal-to-interference plus noise ratio, transponder power consumption, and transponder configuration problem. Simulation results demonstrate that the proposed convex formulation for the transponder configuration problem is considerably faster than its mixed-integer nonlinear counterpart. We consider transmit optical power as a configurable... 

We investigate the problem of energy-efficient resource allocation constrained to quality of service and physical requirements in orthogonal frequency division multiplexing (OFDM)-based elastic optical networks and propose a fast two-stage algorithm to solve it. The first stage of the proposed algorithm deals with routing, traffic grooming, and traffic ordering and mainly aims at minimization of the number of deployed optical amplifiers and transponders. We provide an integer linear program for routing and traffic grooming and propose a heuristic procedure, which yields its near-optimum solution in a shorter runtime. In the second stage, we optimize transponder parameters to minimize total... 

In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and... 

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

In this paper, a simpler implementation of the well-known droop method for the control of parallel Uninterruptible Power Supply (UPS) systems is presented. In this method, in the power-sharing control scheme, the output current is calculated by software without the need for a current sensor, resulting in a simpler and cheaper structure. By doing so, the number of feedback sensors is reduced from three to two. The paralleling strategy uses the droop method in which the control strategy is based on the drop in the inverter output frequency and amplitude. The application of Proportional-Resonant (PR) controllers is also extended to parallel inverter and its superior performance over the... 

In this paper, a new logic style is proposed to be used in the implementation of cryptographic algorithms. The aim of this approach is to counteract power analysis attacks. The proposed technique is based on the transition signaling. In dual-rail transition logic, one-bit value is transmitted by a transition on the proper signal of a couple of wires. According to this concept, converter units and logic gates are defined; it is proposed to use flip-flops to build DTL alternative parts. Although the usage of flip-flops leads to increase the required area, experimental results show that the power consumption of DTL circuits depends on unpredictable initial state of T-flip-flops. In other words,... 

Structural control using energy dissipater devices is emerging as a heavily researched strategy in earthquake engineering. Among several control systems, semiactive control is usually possible and efficient. In this research, a semiactive energy dissipating bracing system based on a viscous damper is proposed. In the conventional bracing systems, it is assumed that the braces can buckle under compression. Therefore, a semiactive on-off brace strategy is implemented to improve the conventional brace performance. Further, an energy absorbing mechanism is implemented. In the proposed system, the buckling of the member is prevented by implementing a one-way valve device. The permanent story... 

This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09- SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering... 

This paper presents a hybrid adaptive network based fuzzy inference system (ANFIS), computer simulation and time series algorithm to estimate and predict electricity consumption estimation. The difficulty with electricity consumption estimation modeling approach such as time series is the reason for proposing the hybrid approach of this study. The algorithm is ideal for uncertain, ambiguous and complex estimation and forecasting. Computer simulation is developed to generate random variables for monthly electricity consumption. Various structures of ANFIS are examined and the preferred model is selected for estimation by the proposed algorithm. Finally, the preferred ANFIS and time series... 

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell,... 

There is growing interest in evaluating the impact of soft errors on multiprocessor system-on-chip (MPSoC) at application-level rather than architectural-level, particularly in multimedia applications to optimize system design. This has recently led to the concept of application-level correctness. In this paper, we consider the relationship between application-level correctness and system-level power management using voltage scaling technique with the aim to generate designs that are optimized in terms of power consumption, while providing acceptable application-level correctness and meeting real-time performance deadlines. We propose a novel voltage scaling technique based on linear... 

The accuracy of the object tracking is dependent on the tracking time interval. Smaller tracking time interval increases the accuracy of tracking a moving object. However, this increases the power consumption significantly. This paper proposes a new adaptive algorithm (AEC) to adapt tracking time interval such that it minimizes power consumption while keeping the required accuracy. Simulation results show that using the proposed algorithm, the tracking network has a good performance with the added advantage of reducing the power consumption significantly when compared with existing nonadaptive methods (like PATES). Moreover, simulation results show that the performance of the proposed... 

A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology. © 2009 IEEE  

Installing smart meters to publish real-time electricity rates has been controversial while it might lead to privacy concerns. Dispatched rates include fine-grained data on aggregate electricity consumption in a zone and could potentially be used to infer a household's pattern of energy use or its occupancy. In this paper, we propose Blowfish privacy to protect the occupancy state of the houses connected to a smart grid. First, we introduce a Markov model of the relationship between electricity rate and electricity consumption. Next, we develop an algorithm that perturbs electricity rates before publishing them to ensure users' privacy. Last, the proposed algorithm is tested on data inspired... 

Internet of Things (IoT) devices have strict necessity for power consumption in order to achieve expected battery life. IoT nodes feature extreme power consumption range over 100 dB, between their operating modes. The main focus of this paper is to design and implement a high precision, high dynamic range, low power, and flexible power measurement system, which can be applied to different applications. The proposed system consists of a voltage regulating control loop, zero offset amplifiers, high precision analog to digital converters, and reference voltage. The proper operation of the proposed circuit are verified numerically with simulations and experimental measurements. The implemented...