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A low power and high density cache memory based on novel SRAM cell

Azizi Mazreah, A ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1587/elex.6.1084
  3. Publisher: 2009
  4. Abstract:
  5. Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell, respectively. © IEICE 2009
  6. Keywords:
  7. Cell area ; Leakage current ; 4T SRAM ; 4T SRAM cell ; 6T SRAM cell ; 6T-SRAM ; Cache access ; Cache access delay ; Cell size ; Design rules ; High density ; ITS data ; Low power ; Low power cache ; Positive feedback ; Power consumption ; SRAM cell ; Static power consumption ; Transistor cells ; Cache memory ; Communication channels (information theory) ; Cytology ; Electric power utilization ; Feedback ; Static random access storage ; Cell membranes
  8. Source: IEICE Electronics Express ; Volume 6, Issue 15 , 2009 , Pages 1084-1090 ; 13492543 (ISSN)
  9. URL: https://www.jstage.jst.go.jp/article/elex/6/15/6_15_1084/_article