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Analysis, Evaluation and Improving the Performance and Power consumption of Mapping and Scheduling algorithms in Network on Chip

Rajaei, Ramin | 2009

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 40555 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Vosoughi Vahdat, Bijan; Hessabi, Shaahin
  7. Abstract:
  8. According to Moor’s law, the number of transistors per chip would double every 1.5 years. It means that the number of processors, memory and hardware cores available on the chip also increases. In SoC, a number of IP cores and communication links or buses are integrated on a chip. According to inefficiency of the interconnection bus used in SoCs for a large number of processors, NoC has been introduced in the beginning of the current decade. In the NoC paradigm a router-based network is used for packet switched on-chip communication among cores. A typical NoC architecture will provide a scalable communication infrastructure for interconnecting cores. One of the most important features of NoCs is reusability. NoC provides maximum possibility for reusability. Mesh topology is one of the simplest NoC topologies implemented till now and is considered in our simulations as a target NoC topology. The NoC architecture for the design should closely match the traffic characteristics and performance requirements of the different applications. Mapping and scheduling are two central and critical steps in overall NoC design flow. They deal with implementation of the applications on NoC. In general, any algorithm designed for Allocation, Assignment and Scheduling takes three basic entities as its input: Application Model (i.e., DAG), Architecture Model (interconnection topology and characterization) and Objective function(s) for optimization (max performance, min power consumption etc).In this dissertation a novel energy aware algorithm for mapping and scheduling of concurrent applications to NoC platforms is developed. The computational resources in NoC consist of a set of heterogeneous IP cores. The introduced algorithm finds a mapping of the vertices of the task graph to available cores so that the overall of energy consumption considering the time constraints of the task graph is minimized
  9. Keywords:
  10. On Chip System ; Network-on-Chip (NOC) ; Scheduling ; MAPS

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