Providing Methods for Reducing and Estimating the Power Consumption of Wireless Networks on Chip

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Shirdel, Mojeeb | 2011

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 42344 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Tabandeh, Mahmoud; Rahemi, Bijan
Abstract:
In recent years, the possibility of building large systems on chip, called SoC is provided. By scaling the technology, designing Socs will face numerous challenges. The Noc paradigm, has resolved many of the SoC’s problems, by deploying network properties in the structures of on chip interconnections. Today, with advances in the semiconductor industry, we can implement broadband wireless antennas, which are integrated on chip. Such NoCs are called WNoC. Due to immaturity of WNoCs, there still exist big challenges, providing routing algorithm and controlling shared medium via MAV layers, for them. In this project, we will provide a routing algorithm based on tag switching, and then, after presenting a synthesizable VHDL description of it, we will try to offer methods for reducing the power consumption of the routers. The same process will be done for a MAC layer algorithm called MACAW. At last, after combining MAC layer and routing algorithm, we will simulate the WNoC, in a program written in MATLAB to obtain network parameters such as throughput, energy and power consumption
Keywords:
Network-on-Chip (NOC) ; Medium Access Control Sublayer ; Throughput ; Low-Power Design ; Tag Switching Method ; Wireless Network-On-Chip (WNoC)

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