Segmented Reconfigurable Bus for SoCs

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Shahidi, Narges | 2010

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 41384 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Sarbazi Azad, Hamid
Abstract:
Advance in VLSI integration level has realized multi-core system-on-chip. For inter-IP communication on-chip network is proposed as a substitute for simple interconnects such as bus fabrics and expensive point-to-point links. Although onchip networks have some superiorities over simple interconnects, but they need more of real estate resource. Although buses are not scalable, they are still popular for their simple communication mechanism. There are so many proposed mechanisms to make buses more scalable and more popular. Most of them try to change bus structure by segmenting and using reconfigurable methods. In this thesis, we explore buses delay by considering the number of component in a bus. Also we propose a method for partitioning the processing units of a task graph. Finally we present a new communication network based on segmented buses. This proposed network makes buses more reconfigurable by changing the structure of segmented buses. Upon running an application program on the network, the configuration of segmented buses can be changed in order to adapt to the partitions of the program
Keywords:
Network-on-Chip (NOC) ; Power Consumption ; Efficiency ; On-Chip Multiprocessor ; Segmented Bus ; Reconfigurability