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Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: A comparative study

Momtazpour, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1049/iet-cdt.2014.0126
  3. Publisher: Institution of Engineering and Technology , 2015
  4. Abstract:
  5. Process variation has already emerged as a major concern in design of multi-processor system on chips (MPSoC). In recent years, there have been several attempts to bring variability awareness into the task scheduling process of embedded MPSoCs to improve performance yield. This study attempts to provide a comparative study of the current variation-aware design-time task and communication scheduling techniques that target embedded MPSoCs. To this end, the authors first use a sign-off variability modelling framework to accurately estimate the frequency distribution of MPSoC components. The task scheduling methods are then compared in terms of both the quality of the final solution and the computational complexity of the scheduling algorithm. Experimental results on a wide range of benchmarks show that ILP-based task scheduling technique, while guaranteeing the optimality of the solution, can be costly for large application task graphs. On the other hand, one-pass heuristic method is 795 times faster than ILP-based method on average, but is ineffective to find reasonable solutions in the case of large task graphs. Finally, metaheuristic approaches can produce near-optimal schedules within 1-2% of the optimal solutions on average, with up to 7.8 times faster execution time compared with ILP-based approach
  6. Keywords:
  7. Benchmarking ; Heuristic methods ; Microprocessor chips ; Multiprocessing systems ; Multitasking ; Optimization ; Scheduling ; Scheduling algorithms ; System-on-chip ; Timing jitter ; Communication scheduling ; Comparative studies ; Frequency distributions ; Improve performance ; Meta-heuristic approach ; Multi processor system on chips ; Variability modelling ; Variation-aware design ; Integrated circuit design
  8. Source: IET Computers and Digital Techniques ; Volume 9, Issue 4 , 2015 , Pages 221-229 ; 17518601 (ISSN)
  9. URL: http://ieeexplore.ieee.org/document/7127133/?arnumber=7127133