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- Type of Document: Ph.D. Dissertation
- Language: English
- Document No: 49825 (52)
- University: Sharif University of Technology, International Campus, Kish Island
- Department: Science and Engineering
- Advisor(s): Miremadi, Ghasem
- Abstract:
- Recent advances in Very-Large-Scale Integration (VLSI) technologies have enabled designers to integrate a large number of Processing Elements (PEs) on a single die. According to International Technology Roadmap for Semiconductors (ITRS), the number of PEs will reach 5000 on a single die in 2021. Although the main achievements of such rapid advancement in chips are high processing speed, shrinkage of technology size has made chips highly sensitive to different challenges. Networks on chip (NoCs), as an example of these systems, are not exempted from these challenges. Crosstalk fault is one of the major fault resources in NoCs. Crosstalk faults occur due to coupling capacitances between parallel and adjacent wires. Crosstalk faults will increase proportional to total wire length. This increase will be serious in the future. It is predicted that the length of total wires would reach to 7000 m/cm^2 until 2020. Unwanted voltage glitches and delay or/and speed up in rising/falling transitions are the main effects of crosstalk faults. The severity of crosstalk faults depends on transition patterns that appear on the tandem flit traversal on wires. Mechanisms at three different levels of design abstraction including 1) physical level, 2) transistor level and, 3) Register Transfer Level (RTL) are proposed to tackle crosstalk fault effects. However, physical and transistor level mechanisms impose high overheads to NoC-based systems. To reduce the overheads of these mechanisms, this dissertation aims to tackle crosstalk faults using data manipulation at RTL. In this regard, to control the effects of transition patterns by proposing data manipulation mechanisms more accurately, first the efficiency of the transition patterns based on 5-wire model is inspected. Then, based on the results of this inspection, Packet/Flit Manipulation (PaFiM) mechanisms and novel overhead-efficient Crosstalk Avoidance Codes (CACs) are suggested. PaFiM includes Packet Manipulation (PAM) and Binary Reflected Gray (BRG) mechanisms. The first mechanism logically rotates the content of every packet using three modes and chooses the packet with minimum number of transitions to be sent to the channel. The second mechanism uses the properties of Gray coding mechanism to find a sequence of flits which generates the lowest number of Triple Opposite Direction (TOD) transition patterns in NoC channels. Then, in order to increase the efficiency of the proposed data manipulation mechanisms and to omit specific transition patterns, five novel lossless and overhead-efficient numerical-based Forbidden Pattern Free (FPF) coding mechanism including Omissive Penultimate-Fibo (OmPe-Fibo), Doubled-Penultimate Fibonacci (DP-Fibo), Iterative-Displaced-Penultimate Fibonacci (IDP-Fibo), Summation-based-Subtracted-Added-Penultimate (S2AP) and Penultimate-Subtracted Fibonacci (PS-Fibo) are proposed. Also, a novel numerical-based OLC called Subtraction-based-Numerical (Sub-Num) is proposed that can reduce the crosstalk faults efficiency. The proposed numeral system-based CACs: 1) can be utilized in NoC channels with any arbitrary width, and 2) can be implemented with low area occupation, power consumption, and timing overheads with respect to the other state-of-the-art CACs. All the proposed mechanisms in this dissertation are evaluated by exhaustive experimental evaluations. Experimental evaluations of the proposed mechanisms reveal significant improvements in the reliability against crosstalk faults in NoCs
- Keywords:
- Reliability ; Network-on-Chip (NOC) ; Crosstalk Fault ; Very Large Scale Integration ; Data Manipulation
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