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Reliability Improvement in Non-Volatile On-Chip Memories for Embedded Applications

Hosseini Monazzah, Amir Mahdi | 2018

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 50560 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghassem
  7. Abstract:
  8. With the technology scaling trend in recent years, leakage power has become a major challenge for SRAM-based on-chip memories. According to the recent reports, SRAM-based on-chip memories contribute to more than half of the processors’ power consumption. Accordingly, in recent years, researchers have tried to find an alternative technology for SRAMs in on-chip memories. The International Technology Roadmap for Semiconductors (ITRS) recently announced that STT-MRAMs are the most promising technology to replace SRAMs. While STT-MRAMs benefit from low energy consumption, high endurance, and high density compared to other non-volatile memory technologies, comparing with SRAMs, STT-MRAMs have several challenges that should be addressed priore being applied across the on-chip memories. Reliability challenges are from imperative challenges of applying STT-MRAMs in on-chip memories. The most important reliability challenges of STT-MRAMs are limited endurance (comparing with SRAMs), read errors, and write failures. These challenges affect STT-MRAM on-chip memories during the access operations. In this thesis, we explore the possible solutions for providing reliable access to STT-MRAM on-chip memories. To this end, we consider the access patterns and data contents of on-chip memories during the run-time of applications. Since embedded systems provide more opportunities to predict the access patterns and data contents of on-chip memories comparing with general porpuse systems, and due to high demands of replacing SRAMs with low-power memory technologies in embedded systems, we focus on embedded application in this study. Our provided approaches can be classified into two groups, content-aware approaches and general (content-unaware) approaches. While we have more opportunity to provide efficient and low overhead methods in content-aware approaches, due to the unpredictable behaviours of access patterns, we also consider general approaches. The evaluation results show up to 100x improvement in endurance limit, up to 57% reduction in read error rate, and up to 10x reduction in write failure
  9. Keywords:
  10. Reliability ; Nonvolatile Memory ; Fault Model ; Spin Transfer Torque-Magnetic (STT-MRAM) ; On-Chip Memories ; Static Random Access Memory (SRAM)Cell

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