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Integrating assertion-based verification into system-level synthesis methodology

Hessabi, S ; Sharif University of Technology | 2004

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  1. Type of Document: Article
  2. Publisher: 2004
  3. Abstract:
  4. In this paper we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can be used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but also run-time verification of system is provided. In this paper, we show the system-level assertions and their synthesis method in our object-oriented system-level synthesis methodology. © 2004 IEEE
  5. Keywords:
  6. Hardware ; System-level design ; Circuit synthesis ; Application specific processors ; Reliability ; Emulation ; Runtime ; Computerized monitoring ; Object oriented modeling ; Embedded system
  7. Source: 16th International Conference on Microelectronics, ICM 2004, Tunis, 6 December 2004 through 8 December 2004 ; 2004 , Pages 232-235
  8. URL: https://ieeexplore.ieee.org/document/1434254