Loading...
| Friend's email | |
| Your name | |
| Your email | |
| enter code | |
This page was sent successfuly
- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 56260 (19)
- University: Sharif University of Technology
- Department: Computer Engineering
- Advisor(s): Sarbazi Azad, Hamid; Hesabi, Shahin
- Abstract:
- The advancement of technology in the semiconductor industry and the resulting increase in the number of transistors on a chip has led to an increase in the number of processing cores an increase in the number of processing cores in a system on chip (SoC). A surge in the number of processing cores, makes their communication more and more noteworthy. This communication is established through the network on chip (NoC). One of the main challenges in NoC design is power management, as it constitutes a high percentage of the overall power consumption of the chip. One of the most power-hungry components of NoC is the router. According to our observation, some of the components of the routers are less utilized compared to the others. Therefore, by using appropriate methods, these components can be reduced or completely removed. This research significantly reduces the complexity of the router by removing some parts of the baseline architecture responsible for implementing turn. Some parts in the proposed method, the dimension change is performed via ejecting the packet in the last step of current dimension and reinjecting it in the first step of the next dimension. The proposed method can easily be extended to an n-dimensional NoC. Additionally, since the proposed method does not suffer from deadlock, any deterministic, semi-adaptive, and adaptive routing algorithms can be used. The proposed architecture results in significant power and area savings in mesh networks with different dimensions
- Keywords:
- System-on-Chip ; Network-on-Chip (NOC) ; Router ; Power Consumption ; Area ; Power Management ; Power Consumption Management
Digital Object List
-
محتواي کتاب
- view
Bookmark