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High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

Jadidi, A ; Sharif University of Technology | 2011

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  1. Type of Document: Article
  2. DOI: 10.1109/ISLPED.2011.5993611
  3. Publisher: 2011
  4. Abstract:
  5. In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache architecture has large capacity and consumes near zero leakage energy using STT-RAM array; while dynamic write energy, acceptable write latency, and long lifetime is guaranteed via SRAM array. Results of full-system simulation for a quad-core CMP running PARSEC-2 benchmark suit confirm an average of 49 times improvement in cache lifetime and more than 50% reduction in cache power consumption when compared to baseline configurations
  6. Keywords:
  7. Hybrid cache architecture ; Spin torque transfer RAM ; Cache architecture ; Cache line displacement ; Chip Multiprocessor ; Wear leveling ; Cache memory ; Electric power utilization ; Flash memory ; Low power electronics ; Memory architecture ; Multiprocessing systems ; Power electronics ; Static random access storage ; Design
  8. Source: Proceedings of the International Symposium on Low Power Electronics and Design, 1 August 2011 through 3 August 2011 ; August , 2011 , Pages 79-84 ; 15334678 (ISSN) ; 9781612846590 (ISBN)
  9. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5993611