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A 6-bit active digital phase shifter

Asoodeh, A ; Sharif University of Technology | 2011

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  1. Type of Document: Article
  2. DOI: 10.1587/elex.8.121
  3. Publisher: 2011
  4. Abstract:
  5. This paper presents the design of a 6-bit active digital phase shifter in 0.18-μm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3±0.9 dBm at 3.5 GHz for overall phase states
  6. Keywords:
  7. Active phase shifter ; All-pass filter ; CMOS technology ; Digital phase shifter ; Input signal ; Phase error ; Phase interpolation ; Phase state ; Phased arrays ; Quadrature network ; Voltage gain ; Wide bandwidth ; CMOS integrated circuits ; Phase shift ; Phase shifters
  8. Source: IEICE Electronics Express ; Volume 8, Issue 3 , 2011 , Pages 121-128 ; 13492543 (ISSN)
  9. URL: https://www.jstage.jst.go.jp/article/elex/8/3/8_3_121/_article