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Systematic modeling and simulation of DLL-based frequency multiplier

Gholami, M ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/SM2ACD.2010.5672340
  3. Abstract:
  4. This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented
  5. Keywords:
  6. Delay locked loop ; DLL ; DLL modeling ; Frequency synthesizer ; Matlab simulink ; Charge pump ; Clock signal ; Delay-locked loops ; Design considerations ; Frequency multiplier ; Input frequency ; Matlab simulink ; Simulation result ; Systematic modeling ; Whole systems ; Computer simulation ; Design ; Frequency multiplying circuits ; Frequency synthesizers ; Integrated circuit manufacture ; Multiplying circuits ; Pumps ; Numerical methods
  7. Source: 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010 ; 2010 ; 9781424468164 (ISBN)
  8. URL: http://ieeexplore.ieee.org/document/5672340