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A nanoscale CMOS SRAM cell for high speed applications

Azizi Mazreah, A ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/ICMENS.2009.47
  3. Publisher: 2010
  4. Abstract:
  5. The leakage current and process variation are drastically increased with technology scaling. In Conventional SRAM cell due to process variations, stored data can be destroyed during read operation. Therefore, leakage current of SRAM cell and stability during read operation are two important parameters in nano-scaled CMOS technology. To overcome these limitations and to increase the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. The developed cell has six-transistors and uses two read/write-lines and two read/write-bit-lines during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The leakage current of new cell is 52% smaller than a conventional six-transistor SRAM cell. Simulation results shows proposed cell has correct operation during read/write and idle modes and is 45% faster than a usual six-transistor SRAM cell
  6. Keywords:
  7. Cell area ; Leakage current ; Process variations ; Read bit-line delay ; Bit lines ; High-speed applications ; Idle mode ; ITS data ; Nanoscale CMOS ; Positive feedback ; Process Variation ; Read operation ; Read static noise margin ; Read/write operations ; Scaled CMOS ; Simulation result ; SRAM Cell ; Static noise margin ; Technology scaling ; Cells ; CMOS integrated circuits ; Cytology ; Feedback ; Leakage currents ; Static random access storage
  8. Source: 5th International Conference on MEMS NANO, and Smart Systems, ICMENS 2009, 28 December 2009 through 30 December 2009, Dubai ; 2010 , Pages 33-36 ; 9780769539386 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/5489261