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A formal approach for debugging arithmetic circuits

Sarbishei, O ; Sharif University of Technology | 2009

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  1. Type of Document: Article
  2. DOI: 10.1109/TCAD.2009.2013998
  3. Publisher: 2009
  4. Abstract:
  5. This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, xor extraction, and carry-signal mapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted xors into half/full-adders to make a very fast debugging algorithm. This approach is robust under multioperand adders, pin-swap techniques, optimizations concerning carry signals or xor terms, and irregularities, such as commutative and associative laws. Moreover, the xor extraction in the proposed algorithm is much faster than conventional techniques, as it does not evaluate the whole netlist. The bugs detected in the partial product initialization and the carry-signal mapping can automatically be replaced with proper logics. However, during the xor extraction phase, the problematic xor s are only reported by the algorithm, and no automatic replacement is performed for such logic gates. To evaluate the effectiveness of our approach, we run it on several arithmetic circuits. © 2006 IEEE
  6. Keywords:
  7. Arithmetic circuits ; Conventional techniques ; Debugging algorithms ; Design issues ; Design optimizations ; Extraction phase ; Formal approaches ; Logic debugging ; Mapping algorithms ; Multioperand adders ; Netlist ; Partial products ; Postsynthesis verification ; Run-time ; Signal mappings ; Three phasis ; Adders ; Algorithms ; Conformal mapping ; Integrating circuits ; Sequential circuits ; Program debugging
  8. Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 28, Issue 5 , 2009 , Pages 742-754 ; 02780070 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/4838829