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SRAM Cell Design for Low Power Applications

Ganji, Mona | 2017

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 51298 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Haj Sadeghi, Khosrow
  7. Abstract:
  8. From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of the popular methods in power consumption reduction for SRAMs is to operate these memory units in subthreshold region. However, lowering the operating voltage, rises the soft error rate. Bit-interleaving is the primary and most feasible solution for eliminating soft errors. Performing bit-interleaving technique requires exclusive access to each bit cell. Other remedy to improve power consumption is to optimally design the structure of the memory unit and peripheral circuits such as sense amplifier and address decoders. In this thesis, a novel six transistor SRAM cell is proposed according to the design limitations and preferences for SOCs. The proposed 6T cell designed in 90 nm technology, is operational down to 200 mv and utilizes one bitline to reduce dynamic power consumption. An 8T SRAM cell in same technology node is also proposed with Bit-interleaving capability and working ability in subthreshold region. A 2D memory structure of 4Kb is introduced that reduces the number of the needed address decoders by one fourth compared to the conventional structure. Also, an address decoder is proposed taking advantage of selective precharge idea, in order to reduce the dynamic power consumption. The proposed address decoder consumes nearly 25× less power in comparison to conventional NOR decoder. The 2D structure of 4Kb with proposed selective address decoder shows 42% better power performance compared to the same size conventional structure with NOR address decoder. For an attentive comparison, a 4Kb memory unit of proposed 6T cell in 90 nm technology is considered and its complete layout is carried out. The post layout simulation with extracted parasitic capacitors of the chip shows 6.5× better power performance compared to conventional overall memory structure with conventional bitcell in same operating voltage and 30× less power consumption in subthreshold region
  9. Keywords:
  10. Soft Error ; Static Random Access Memory (SRAM)Cell ; Subthreshold ; On Chip System ; Low-Power Design ; Power Reduction

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