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Design of a 2-12-GHz bidirectional distributed amplifier in a 0.18- mu m CMOS technology

Alizadeh, A ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TMTT.2018.2883956
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm 2 die area, and its average measured noise figure and P-{ ext {dc}} are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively. © 1963-2012 IEEE
  6. Keywords:
  7. Bidirectional amplifiers (BDAs) ; Bidirectional distributed amplifiers (BDDAs) ; CMOS integrated circuits ; Distributed amplifiers (DAs) ; Integrated circuit design ; Noise figure ; 1dB compression point ; Bidirectional amplifiers ; CMOS technology ; DC power consumption ; Design and implementations ; Distributed amplifier ; Low power modes ; Small signal gain ; Broadband amplifiers
  8. Source: IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 2 , 2019 , Pages 754-764 ; 00189480 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8574995