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A power efficient approach to fault-tolerant register file design

Amiri Kamalabad, M ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1109/VLSI.2008.53
  3. Publisher: 2008
  4. Abstract:
  5. Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an OpenRISC 1200 processor. The experimental calculation of the power consumption shows that the proposed approach saves about 67%, 62%, and 58% power for TMR, duplication with parity, and SEC hamming code, respectively. © 2008 IEEE
  6. Keywords:
  7. Arsenic compounds ; Codes (standards) ; Codes (symbols) ; Electric power utilization ; Error correction ; Fault tolerant computer systems ; Quality assurance ; Reliability ; Case studies ; Dynamic power ; Embedded processors ; Fault-tolerant ; Hamming codes ; International conferences ; Power consumption ; Power efficient ; Power reductions ; Register files ; Techniques used ; Transient faults ; Triple modular redundancy (TMR) ; VLSI designs ; Fault tolerance
  8. Source: Proceedings of the IEEE International Frequency Control Symposium and Exposition, 4 January 2008 through 8 January 2008, Hyderabad ; 2008 , Pages 21-26 ; 0769530834 (ISBN); 9780769530833 (ISBN)
  9. URL: https://www.computer.org/csdl/proceedings-article/vlsid/2008/30830021/12OmNqzu6Mm