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Fast co-verification of HDL models

Asadi, G ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1016/j.mee.2006.02.007
  3. Publisher: 2007
  4. Abstract:
  5. This paper presents a method for functional verification of HDL models of digital circuits. The method is based on a co-operation between a simulator and an emulator and utilizes the advantages of both simulation-based and emulation-based verification to form a fast co-verification approach. This is done by verifying the intensive time-consuming part of the circuit in the emulator and the non-synthesizable part as well as the part of the circuit that needs intensive redesign process during the early steps of the design phase in the simulator. To demonstrate the co-verification approach, a tool was developed, which supports Verilog, VHDL, and mixed Verilog-VHDL models. Three benchmarks including a simple 32-bit processor (DP32), a 16-bit arithmetic RISC processor, and a 256-point FFT unit were used in the experiments. The experimental results show that the co-verification approach gives up to 15,000 times speedup for gate-level and up to 100 times speedup for RTL abstractions as compared with the simulation-based verification. Finally, an analytical study on the speedups of the co-verification approach is also presented, which supports the experimental speedups results. © 2006 Elsevier B.V. All rights reserved
  6. Keywords:
  7. Computer simulation ; Digital circuits ; Fast Fourier transforms ; Simulators ; Emulation ; Emulators ; Hardware verification ; RISC processors ; Computer hardware description languages
  8. Source: Microelectronic Engineering ; Volume 84, Issue 2 , 2007 , Pages 218-228 ; 01679317 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0167931706003029